ASIC verification jobs - Irvine, CA
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| Nov 05 | Sr. Systems Engineer | Irvine, CA | |
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*? Closely work with system, firmware and ASIC engineers. Provide test vectors and technical support for debugging and verification on FPGA. Requirements: *? MSEE plus minimum of... more |
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| Nov 04 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be responsible ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Nov 04 | Staff Scientist | Broadcom | Irvine, CA |
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Category : Engineering Position Type : Verification Shift : 1st shift - ... parameter test of broadband Mix-signal ASIC using laboratory bench equipments... more |
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| Nov 04 | DFT Manager | Broadcom | Irvine, CA |
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Engineer to perform any of the following ASIC design tasks: - Plan/coordinate/manage ... DFT functional verification, DFT coverage verification and static timing analysis. -... more |
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| Nov 04 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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5+ years of RTL (Verilog) design and verification of ICs * Able to make system ... Blocks and RTL * Knowledge of entire ASIC design methodology flow including:... more |
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| Nov 04 | Intern, Engineering | Broadcom | Irvine, CA |
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test equipments and devices for device verification test. - Perform post-silicon ... high speed SERDES read channel Mix-signal ASIC. - Document test setup information and... more |
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| Nov 04 | Sr. Systems Engineer | Irvine, CA | |
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*? Closely work with system, firmware and ASIC engineers. Provide test vectors and technical support for debugging and verification on FPGA. Requirements: *? MSEE plus minimum of... more |
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| Nov 02 | Hardware Engineer, Electronic Engineer, FPGA, Acte | Cybercoders | Long Beach, CA |
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Skills Required - FPGA, Actel, anti fuse, Asic, PCI Bus Protocol, Electronic Engineer, ... the cards, card and system level debug and verification. - Support the cards/systems... more |
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| Oct 31 | DFT Manager | Broadcom | Irvine, CA |
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Engineer to perform any of the following ASIC design tasks:- Plan/coordinate/manage ... DFT functional verification, DFT coverage verification and static timing analysis.-... more |
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| Oct 28 | DFT Manager | Broadcom | Irvine, CA |
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Engineer to perform any of the following ASIC design tasks:- Plan/coordinate/manage ... requirements, this includes DFT functional verification, DFT coverage verification and... more |
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| Oct 25 | DFT Manager | Broadcom | Irvine, CA |
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DFT functional verification, DFT coverage verification and static timing analysis. - ... must possess the following skills: - ASIC design & implementation experience with... more |
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| Oct 24 | DFT Manager | Broadcom | Irvine, CA |
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Engineer to perform any of the following ASIC design tasks: - Plan/coordinate/manage ... DFT functional verification, DFT coverage verification and static timing analysis. -... more |
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| Oct 23 | System Engineer | Maxim Integrated Products | Irvine, CA |
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and technical support for debugging and verification on FPGA. Requirements: * MSEE plus minimum of 6 years experience required or PhD with minimum of 4 years experience. * Good... more |
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| Oct 22 | DFT Manager | Broadcom | Irvine, CA |
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requirements, this includes DFT functional verification, DFT coverage verification and ... must possess the following skills: - ASIC design & implementation experience with... more |
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| Oct 19 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be responsible ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Oct 14 | Lead / Architect ASIC Design Engineer | Recruitment Call | Irvine, CA |
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nt digital communication system blocks which include: o Specification trade-offs and optimization o Micro-architecture o RTL coding o Simulation and verification o Chip testing... more |
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| Oct 13 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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5+ years of RTL (Verilog) design and verification of ICs* Able to make system ... Blocks and RTL* Knowledge of entire ASIC design methodology flow including:... more |
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| Oct 09 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Oct 08 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Oct 08 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be responsible ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Oct 08 | ASIC Design Enginner with Security Clearance | SafeNet Government Solutions | Irvine, CA |
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development, architecture definition, ASIC specification, HDL (Hardware ... creating simulation and prototype verification test plans, conduction hardware... more |
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| Oct 07 | ASIC Design Engineer | SafeNet Gsd | Irvine, CA |
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definition/planning, implementation/verification and test portions of the ISO 9001 ASIC ... architecture definition, ASIC specification, HDL (Hardware Description... more |
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| Oct 07 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be responsible for understanding and delivering standardize LVS, DRC, ERC, ANT, DFM technology files for... more |
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| Oct 05 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Sep 26 | Staff Scientist | Broadcom | Irvine, CA |
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Category : Engineering Position Type : Verification Shift : 1st shift - ... parameter test of broadband Mix-signal ASIC using laboratory bench equipments... more |
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| Sep 25 | Principal ASIC Design Engineer | Broadcom | Irvine, CA |
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You may also be involved in system modeling and performance verification using C/C++ or ... Experienced in ASIC/VLSI design and verification... more |
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| Sep 25 | Senior ASIC Design Engineer | Broadcom | Irvine, CA |
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will be used to derive the final product. Verification of this work is essential so ... or any synthesis experience,Formal Verification experience City : Irvine State... more |
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| Sep 25 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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5+ years of RTL (Verilog) design and verification of ICs* Able to make system ... Blocks and RTL* Knowledge of entire ASIC design methodology flow including:... more |
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| Sep 24 | Principal ASIC Design Engineer | Broadcom | Irvine, CA |
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You may also be involved in system modeling and performance verification using C/C or ... --- Experienced in ASIC/VLSI design and verification... more |
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| Sep 24 | Senior ASIC Design Engineer | Broadcom | Irvine, CA |
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will be used to derive the final product. Verification of this work is essential so ... or any synthesis experience o Formal Verification experience City :... more |
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| Sep 24 | Staff Scientist | Broadcom | Irvine, CA |
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- Perform and lead the bench testing of ASIC electrical parameters across multiple ... parameter test of broadband Mix-signal ASIC using laboratory bench equipments... more |
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| Sep 15 | Electrical Engineer-Entry Level | Rockwell Collins | Irvine, CA |
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for engineering build, test, design verification, design documentation, and ... software, systems, RF, mechanical, FPGA and ASIC, Design To Cost, Producibility, etc. more |
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| Sep 10 | Physical Verification IC Engineer | Broadcom | Irvine, CA |
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End ASIC Design for IP Group - The physical Verification Engineer will be responsible ... in VLSI circuit design, simulation, verification, timing analysis. Possess deep... more |
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| Sep 10 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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5+ years of RTL (Verilog) design and verification of ICs * Able to make system ... Blocks and RTL * Knowledge of entire ASIC design methodology flow including:... more |
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| Sep 10 | Intern, Engineering | Broadcom | Irvine, CA |
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- Setup/configure bench test equipments and devices for device verification test. - ... high speed SERDES read channel Mix-signal ASIC. - Document test setup information and... more |
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| Aug 30 | Manager IC Design | Broadcom | Irvine, CA |
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DFT functional verification, DFT coverage verification and static timing analysis.- ... must possess the following skills:- ASIC design & implementation experience with... more |
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| Aug 25 | Intern, Engineering | Broadcom | Irvine, CA |
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Description : - Setup/configure bench test equipments and devices for device verification ... high speed SERDES read channel Mix-signal ASIC.- Document test setup information and... more |
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| Aug 21 | Intern, Engineering | Broadcom | Irvine, CA |
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Description : - Setup/configure bench test equipments and devices for device verification ... high speed SERDES read channel Mix-signal ASIC. - Document test setup information and... more |
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| Aug 20 | Intern, Engineering | Broadcom | Irvine, CA |
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test equipments and devices for device verification test. - Perform post-silicon ... high speed SERDES read channel Mix-signal ASIC. - Document test setup information and... more |
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| Aug 18 | Intern, Engineering | Broadcom | Irvine, CA |
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test equipments and devices for device verification test. - Perform post-silicon ... high speed SERDES read channel Mix-signal ASIC. - Document test setup information and... more |
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| Aug 06 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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* 5+ years of RTL (Verilog) design and verification of ICs * Able to make system ... Blocks and RTL * Knowledge of entire ASIC design methodology flow including:... more |
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| Jul 12 | Principal IC Designer | Menara | Irvine, CA |
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to the Vice-President for ASIC Development, the successful candidate will be a ... capture, layout, mixed-mode simulation, verification and parasitic extraction tools... more |
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| Jul 03 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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5+ years of RTL (Verilog) design and verification of ICs * Able to make system ... Blocks and RTL * Knowledge of entire ASIC design methodology flow including:... more |
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| Jun 22 | Senior Digital IC Design Engineer | Broadcom | Irvine, CA |
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* 5+ years of RTL (Verilog) design and verification of ICs * Able to make system ... Blocks and RTL * Knowledge of entire ASIC design methodology flow including:... more |
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| Apr 24 | Excellent Opportunities for Entry-Level Engineers! | Western Digital | Lake Forest, CA |
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digital ASIC architecture and functional verification in Advanced Concepts Development. FIT Engineer Primary responsibility: The Functional Integrity Testing lab develops tests... more |
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