ASIC verification jobs - Monte Sereno, CA
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| Nov 23 | Sr. Verification Engineer | Brocade Communications Systems | San Jose, CA |
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through several complete and successful ASIC design/verification cycles from ... and Experience?8 ? 10 years of ASIC verification experience. ?Strong... more |
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| Nov 22 | ASIC Design and Verification Engineer, Senior | Silicon Image | Sunnyvale, CA |
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ASIC design and verification engineer who involves in various steps of ASIC ... and industrial experience on Verilog based ASIC design and verification MUST HAVE - RTL... more |
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| Nov 22 | Engineer, ASIC Design | Marvell Technology Group | Santa Clara, CA |
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Perform RTL coding. * Perform functional verification of design on block and system level. * Perform synthesis and timing closure. * Perform SCAN insertion and ATPG generation. *... more |
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| Nov 21 | High Speed : CPU Designer | Modicom | San Jose, CA |
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ASIC experience with 7+ years of Networking ASIC experience. --You should have been ... Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). more |
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| Nov 20 | Senior ASIC Design Engineer - Storage | Modicom | San Jose, CA |
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ASIC Design Engineer - StorageRequirements:--Define the architecture of new ... simulation and verifications designs --ASIC test and debugging... more |
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| Nov 20 | Senior ASIC Design Engineer - Storage | Modicom | San Jose, CA |
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ASIC Design Engineer - Storage Requirements: --Define the architecture of new ... simulation and verifications designs --ASIC test and debugging Qualifications:... more |
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| Nov 20 | High Speed : CPU Designer | Modicom | San Jose, CA |
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ASIC experience with 7+ years of Networking ASIC experience. --You should have been ... Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). more |
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| Nov 20 | Engineer, Sr. Staff Physical Design... | Broadcom | Sunnyvale, CA |
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Be part of the world class ASIC physical design team, contributing to ... static timing analysis, physical verification (DRC/LVS/ERC). Qualifications: BSEE... more |
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| Nov 19 | ASIC Physical Design Engineer | Techforce | San Jose, CA |
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Implementation of multimillion gate ASIC designs in cutting edge process ... experience. Chip level P&R, Physical Verification, Synopsys IC Compiler, Magma... more |
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| Nov 19 | Engineer, ASIC Design | Marvell | Santa Clara, CA |
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Title: Engineer, ASIC Design Job Category: Engineering Job Sub Category: Digital ... methodologies, understands all stages of ASIC design flows, and is experienced with... more |
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| Nov 18 | ASIC Verification Engineer | Cross Creek Systems | Sunnyvale, CA |
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VERIFICATION, CADENCE, PROCESS, ARCHITECT, ASIC, COMPUTER SCIENCE, ENGINEER, LINUX, PERL, SCRIPTING LANGUAGES, SOFTWARE, TEST, TOOLS, VERILOG, architecture, ELECTRICAL ENG, MEDIA,... more |
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| Nov 18 | Senior Verification Engineer | Cross Creek Systems | Campbell, CA |
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processors. Using various techniques of ASIC verification and software/embedded ... environments and test benches for ASIC verification Development of behavioral... more |
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| Nov 18 | Engineer, Senior ASIC Design | Marvell Technology Group | Santa Clara, CA |
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Perform RTL coding. * Perform functional verification of design on block and system level. * Perform synthesis and timing closure. * Perform ATPG pattern generation. * Provide... more |
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| Nov 18 | Sr. Verification Designer | Cross Creek Systems | Santa Clara, CA |
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Minimum of +7 years ASIC design experience Verification experience either on ... verification strategies on complex ASIC SoC Hands-on experience in delivering... more |
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| Nov 18 | ASIC MAC Design Engineer | Cross Creek Systems | Palo Alto, CA |
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code integration, SCAN insertion, system verification support, back-end physical ... and tape-out preparation Help recruit talented ASIC designers and verification... more |
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| Nov 18 | ASIC PHYSICAL DESIGN MANAGER | Cross Creek Systems | Palo Alto, CA |
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an ASIC hands on physical design manager, you will be responsible for the physical ... ASICs. You will define physical design and verification methodologies. You will... more |
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| Nov 18 | Senior ASIC/VLSI design Engineer (backend) | Cross Creek Systems | Campbell, CA |
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enhancement, verify (physical and logical verification) and "productize" complex ... years of ASIC design and verification experience Proficient in... more |
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| Nov 18 | Senior ASIC/VLSI design Engineer (frontend) | Cross Creek Systems | Campbell, CA |
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services, etc. Requirements: 8+ years of ASIC design and verification ... assertion-based verification, formal verification model checking, etc. more |
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| Nov 18 | Senior ASIC Design Engineer - CMOS Image Sensors (location: Irvine, California) | Tfi | San Jose, CA |
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(location: Irvine, California), Senior ASIC Design Engineer (CMOS Image Sensors) ... System Verilog or assertion based verification background. Knowledge of ISP... more |
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| Nov 18 | IC Digital Designer | Cross Creek Systems | Cupertino, CA |
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ASIC experience with 4+ years of Networking ASIC experience. You should have been ... Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). more |
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| Nov 18 | Senior Chip Design Engineer | Cross Creek Systems | Campbell, CA |
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enhancement. Requirements: 8+ years of ASIC design and verification ... speed interfaces. Experience using modern verification techniques Proven experience in... more |
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| Nov 18 | Global Circuits and Chip Integration Engineer | Cross Creek Systems | Sunnyvale, CA |
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of experience in high performance custom or asic chip design. Successful candidate will ... integration, electrical and timing verification, cell selection and... more |
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| Nov 18 | Network Systems Architect | Cross Creek Systems | Cupertino, CA |
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in the following areas is desired: ASIC design tools and flow Metropolitan area ... specification, design, implementation and verification of large, complex integrated... more |
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| Nov 18 | Engineer, Sr. Staff Physical Design | Broadcom | Sunnyvale, CA |
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to enterprise. Be part of the world class ASIC physical design team, contributing to ... and route, static timing analysis, physical verification (DRC/LVS/ERC). Job Requirements... more |
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| Nov 17 | Sr. ASIC Verification Engineer | Redback Networks | San Jose, CA |
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ASIC Verification Engineer San Jose, CA (no relo or 3rd parties please) The ... At least 7-10+ years experience of ASIC verification and/or performance modeling*... more |
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| Nov 17 | Verification engineer(System Verilog) | Synapse Design Automation | San Jose, CA |
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Requirements: Verification of multi-million gate ASIC/SOC. Must be an expert with System Verilog, Vera or System C IP or domain experience is important including ARM, SAS/SATA,... more |
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| Nov 17 | Engineer, Sr. Staff Physical Design | Broadcom | Sunnyvale, CA |
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to enterprise. Be part of the world class ASIC physical design team, contributing to ... and route, static timing analysis, physical verification (DRC/LVS/ERC). Job Requirements... more |
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| Nov 16 | Sr. ASIC Verification Engineer | Redback Networks | San Jose, CA |
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ASIC Verification Engineer San Jose, CA (no relo or 3rd parties please) The ... have At least 7-10+ years experience of ASIC verification and/or performance... more |
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| Nov 16 | SOFTWARE DEVELOPMENT MANAGER | Canesta | Sunnyvale, CA |
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chips to full production including design, verification, physical design and post ... products * Experience delivering custom ASIC-based high-volume low-cost consumer... more |
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| Nov 16 | DIRECTOR OF SILICON ENGINEERING | Canesta | Sunnyvale, CA |
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specification & architecture, design, verification, physical design, post silicon ... knowledge of developing mixed signal ASIC flows, specifying & successfully... more |
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| Nov 16 | Engineer, Sr. Staff Physical Design | Broadcom | Sunnyvale, CA |
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to enterprise. Be part of the world class ASIC physical design team, contributing to ... and route, static timing analysis, physical verification (DRC/LVS/ERC). Job Requirements... more |
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| Nov 15 | SENIOR EMULATION ENGINEER | NVIDIA | Santa Clara, CA |
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5+ years experience in emulation, design verification, or ASIC design- Requires fluency in verilog and C++.- Familiarity with PC architecture and standard interfaces- Experience... more |
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| Nov 14 | ASIC Verification Engineer - Acceleration | Broadcom | Santa Clara, CA |
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and scalable Perl script automation of verification techniques. RTL verification ... simulator Experience with large SOC design verification FPGA/hardware accelerator... more |
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| Nov 14 | ASIC Design and Verification Engineer, Senior | Silicon Image | Sunnyvale, CA |
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ASIC design and verification engineer who involves in various steps of ASIC ... and industrial experience on Verilog based ASIC design and verification MUST HAVE - RTL... more |
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| Nov 14 | Engineer, Sr. Staff Physical Design | Broadcom | Sunnyvale, CA |
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to enterprise. Be part of the world class ASIC physical design team, contributing to ... and route, static timing analysis, physical verification (DRC/LVS/ERC). BSEE with nine... more |
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| Nov 14 | Engineer, Sr. Staff Physical Design | Broadcom | Sunnyvale, CA |
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to enterprise. Be part of the world class ASIC physical design team, contributing to ... and route, static timing analysis, physical verification (DRC/LVS/ERC). Job Requirements... more |
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| Nov 13 | ASIC Verification Engineer | Micron Technology | San Jose, CA |
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an ASIC Verification Engineer in the Flash Systems Group at Micron Technology, Inc., ... track record for successful verification of ASIC products in the past. * A strong... more |
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| Nov 13 | ASIC Verification Engineer | Brocade Communications Systems | San Jose, CA |
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work for every aspect of ASIC verification, working closely with the ... through several complete and successful ASIC design/verification cycles from... more |
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| Nov 13 | ASIC Verification Engineer - Acceleration | Broadcom | Santa Clara, CA |
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and scalable Perl script automation of verification techniques. RTL verification ... protocols, datapath validation, processor verification, and networking protocols. more |
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| Nov 13 | ASIC Verification Engineer - Acceleration | Broadcom | Santa Clara, CA |
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Number : 09-11934 Job Title : ASIC Verification Engineer - Acceleration Job ... and scalable Perl script automation of verification techniques. RTL verification... more |
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