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Jul 15 Client Account Manager for Fast Growing I.T. Support Firm Computer Solutions Group Los Angeles, CA

accessible through the service management systemc. Ensure all procedures are followed and documented as required4. Technical Productivitya. Achieve company defined objectives for... more

Jul 08 Principal EDA Software Engineer CAE Recruiters San Jose, CA

abstract specifications written in C++/SystemC and their corresponding RTL implementations and contributing to leading edge software development for this tool. This will involve... more

Jun 27 Verification Engineers Ee-recruiters Santa Clara, CA

tools desiredSkills that are pluses:- C++ or SystemC programmingWhat you'll be doing:- ... Verification, SystemVerilog, OVM / UVM / or VMM, C++ or SystemC, "verification... more

Jun 22 Principal Engineer / Architect Florentina Fox Agency Palo Alto, CA

in MatLab, Verilog & SystemC is highly desirable. Experience in optimizing algorithms & C for multi-core implementation highly desirable. •A history or active participation in... more

Jun 18 C++ Tutoring/Teaching Wyzant Tutoring Aurora, CO

I am anew student in a c++ course. My problem is navigating UNIX and the univ systemC++ Tutoring & Teaching opportunities available in Aurora, CO starting at $25-$50/hr. more

Jun 16 Design Verification Engineers Collabera San Diego, CA

debugging skills. Basic knowledge of SystemC TLM (transaction level modeling) ... (DPI) functions for calling C++ and systemC functions from System Verilog UVM... more

Jun 08 Speech Micro - Architect Intel Santa Clara, CA

in SystemVerilog - Familiarity with SystemC modelling and/or scripting. - Familiarity with a range of Internal and 3rd-Party Logic Design/validation Tools. Preferred... more

Jun 05 Product Validation Engineer/ Sr Member of Technical Staff /T3 Cadence Design Systems Chelmsford, MA

SoC Verification, with a Hardware Verification Language (HVL) like systemC/ Vera or SystemVerilog is a strong match for this position. The person should have a track record in... more

May 29 Senior ASIC Engineer - DSP Cybercoders Santa Ana, CA

Hands on experience with C/C++, SystemC and/or Matlab a plus - Hands on RTL Design, Debug, verification - Strong hands on STA, Synthesis, DFT, LEC, Formal Verification, BIST,... more

May 29 Analog Design Engineer Cybercoders Mountain View, CA

- Behavioral modeling with System Verilog, SystemC, Matlab and other languages - Worked in a Cadence or similar environment What's In It for You - Well-Funded, Exciting, and... more

May 29 Analog IC Engineer Cybercoders Mountain View, CA

- Behavioral modeling with System Verilog, SystemC, Matlab and other languages - Worked in a Cadence or similar environment What you'll be doing: - You will be involved with the... more

May 26 Electrical Engineer - Consumer Electronics Survios Los Angeles, CA

experience with design verification using SystemC, SystemVerilog or similarExperience with verification and debugging tools such oscilloscope, multimeter, signal and spectrum... more

Apr 25 Sr Application Engineer Cadence Design Systems San Jose, CA

with a mix of SystemVerilog, SystemC/C/C++, Verilog & VHDL using industry ... SystemVerilog, VHDL, Verilog, C/C++, SystemC * Experience with debug of UVM * Ability... more

Apr 23 Principal Application Engineer Cadence Design Systems San Jose, CA

environments utilizing SystemVerilog, e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience creating a Verification Plan and using verication management tools... more

Apr 07 Staff Application Engineer Cadence Design Systems Austin, TX

environments utilizing SystemVerilog, e or SystemC/C++ . Looking for System Verilog and UVM skills. Experience creating a Verification Plan and using verication management tools... more

Jan 29 Principal R&D Application Engineer Cadence Design Systems San Jose, CA

programming and system simulation using SystemC is a plus * Must have excellent written and verbal communication skills as well as good problem solving skills. * Able to travel... more

Dec 03 Lead Verification Engineer, SoC Cadence Design Systems Austin, TX

Formal (Assertion) Based Verification * SystemC, TLM1.0/TLM2.0 experience * ARM Processor knowledge * Digital Design experience * Other standard bus protocol knowledge (i.e. more

More Job Postings from the Web
Jul 24 SIP Pre-Si Verification Engineer Intel California

Experience with software like C, C , SystemC advantage Experience with validation of interconnects/fabrics would be added value. Experience with System Verilog, OVM/Saola... more

Jul 23 Sr. Video Architect Apple California

of c-modeling tools, including C/C++, SystemC and scripting languages such as Perl and/or Python * Knowledge of video coding standards including MPEG-4, H.264, HEVC * Knowledge of... more

Jul 23 Intern - Network Switch Arch Performance (Fall 2014) Classifiedads.com San Jose, CA

Experience with a simulation tool such as SystemC/NS-2/Omnet++ **Country** US **State/Province** CA **City/Town** San Jose **Shift** 1st Shift - Day **Percent of Travel... more

Jul 22 Engineer Circuit Design- 4 (Job Nbr 14006467) PDS Tech Redondo Beach, CA

PDS is seeking a Engineer - Circuit Design for an open position in Redondo Beach, CA. In ... functional coverage using PSL or SVA, and modeling using C/C++, SystemVerilog, or... more

Jul 12 Senior Design Modeling Engineer Encore Semi San Diego, CA

for implementing and supporting C++ and SystemC functional models for the Digital ... video codec protocols• SystemC TLM 2.0 experience• Design and verification environment... more

Jul 10 Instant Closure Need Pre-Silicon Engineer @ Simplion Technologies Milpitas, CA

) or Memory Interfaces ( Flash, DDR, SDIO etc ) or SoC infrastructure blocks ( Bus Infrastructure, DMA etc ).Experience in emulation / systemc is a plus. Good communication... more

Jul 09 MTS ASIC/ Layout Design Engineer AMD Sunnyvale, CA

SV/VMM, SV, C++, SystemC, Vera, E)
• Mastery of a scripting language (Shell, Perl, Python, Ruby)
• Verification functional coverage using industry standard coverage analysis... more

Jul 08 Design Verification Engineer Amd | Seamicro Sunnyvale, CA

functional modeling using C and SystemC preferred • Familiarity with System Verilog and OVM/UVM preferred • Experience with build tools including make, version control, LSF, Perl,... more

Jun 30 Intern - Network Switch Arch Performance (Fall 2014) Broadcom San Jose, CA

2. Experience with a simulation tool such as SystemC/NS-2/Omnet++ Country US State/Province CA City/Town San Jose Shift 1st Shift - Day Percent of Travel Required None Function... more

Jun 28 Staff ASIC Verification Engineer Results Center Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Jun 27 Verification Engineer II Job SanDisk Milpitas, CA

include: Developing behavioral models in SystemC and C++ and methodology development for logic design and verification. Evaluation of new RTL design tools and flows. Support of... more

Jun 27 Staff ASIC Verification Engineer Marvell Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Jun 26 Terminal Manager Philadelphia, PA

L.b) Monitor the terminal Quality Management Systemc) Review delivery schedule to ensure customers requirements are met.d) Responsible for the training and professional... more

Jun 26 Staff ASIC Verification Engineer Cameron Resources Group Sunnyvale, CA

with functional modeling using C++ and SystemC Familiarity with System Verilog and OVM/UVM Experience with build tools including make, version control, LSF, Perl, or Ruby... more

Jun 23 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of Science degree in Electrical or Computer Engineering with a minimum 9 years of relevant experience or 7... more

Jun 09 Senior Principal Analog Design Engineer Terran Systems San Jose, CA

with analog behavioral modeling a plus (SystemC, System Verilog, Matlab) ? Self driven, results -oriented individual capabile of working well with a very experienced and proven... more

Jun 05 Lead Member Technical Staff Mentor Graphics Incorporation Indiana

to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of bus protocols like AMBA, PCIe, USB will be an advantage. Job Qualifications: The person will be... more

Jun 05 Lead Member Technical Staff Mentor Graphics Indiana

to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of bus protocols like AMBA, PCIe, USB will be an advantage. Job Qualifications: The person will be... more

Jun 03 CPU Model Engineer Artisan Austin, TX

microarchitecture * Prior knowledge of SystemC / TLM2 would be an advantage General Attributes It is essential for the successful applicant to: * Demonstrate enthusiasm, drive... more

Jun 03 CPU Model Engineer Middlesex Community College Austin, TX

microarchitecture * Prior knowledge of SystemC / TLM2 would be an advantage General Attributes It is essential for the successful applicant to: * Demonstrate enthusiasm, drive... more

May 29 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Communications Camden, NJ

proficiency in C/C++, VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired but not required. Knowledge of high-speed peripheral interfaces... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

proficiency in C/C , VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired but not required. Knowledge of high-speed peripheral interfaces... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

ec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC, Scripting language Tools:... more

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