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Sep 10 Electronic System-Level (ESL) Modeler (SystemC, SoC) HCL America Hillsboro, OR

(as many) Hardware modelling using (SystemC, C++, DML, TLM Standards, HDL) OSCI, ... and verifiable professional experience. systemc c c++ esl tlm microprocessor... more

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Sep 16 Patient Care Assistant St. Luke's University Health Network Coaldale, PA

orders using order entry computer systemc) Maintains sufficient unit suppliesd) Maintains unit statistics, manuals and logs as assignede) Communicates between members of the... more

Sep 13 FPGA/ASIC Engineer General Dynamics Arizona

C/C++, Perl, and UNIX. Proficiency with SystemC and a big plus. Knowledge of OVM, UVM or VMM is required. Knowledge of high-speed peripheral interfaces (PCI/SpaceWire, SERDES,... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

include: Developing behavioral models in SystemC and C++ and methodology development for logic verification. RTL and Gate level simulation/verification. Support of assertions and... more

Sep 11 Product Engineering SW Architect - Semi and System Software Wipro Portland, OR

Embedded SW, C++, SystemC/ TLM2/ Perl/ Python/ Basic Architecture concepts, SW processes?Basic ISA modeling / IP Modeling / Writing Tests / AutomationSOC Modeling ( Func / Cycle... more

Sep 11 CPU Model Engineer Middlesex Community College Austin, TX

microarchitecture * Prior knowledge of SystemC / TLM2 would be an advantage It is essential for the successful applicant to: * Demonstrate enthusiasm, drive and diligence * Work... more

Sep 11 Senior ASIC Verification Engineer Results Center Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Sep 11 Senior ASIC Verification Engineer Marvell Santa Clara, CA

Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments... more

Sep 11 Design Verification and Methodology Deployment Engineer Encore Semi San Diego, CA

languages: C, C++, and SystemC. • Experience in functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is highly desired. • Scripting and... more

Sep 09 Computer Algorithms Automatic Speech recognition Intouch Staffing Professionals Sunnyvale, CA

scripting experience middot Knowledge of SystemC US Citizens and all other parties authorized to work in the US are encouraged to apply. We are unable to sponsor H1B Visarsquos at... more

Sep 08 Staff R&D Simulation Tools Engineer Synopsys Sunnyvale, CA

new features for the transaction level SystemC models as well as cycle accurate ... Experience with SystemC 2.x, OSCI SystemC, TLM 2.0 API standards a plus ·... more

Sep 08 Intern- Firmware/Microcode Job Micron Boise, ID

- Contributing to the architecture of SystemC models of the Advanced Memory Systems ... software development tools, debuggers, SystemC, and simulation techniques is a plus. more

Sep 05 Verification Engineer Ee-recruiters Santa Clara, CA

desired Skills that are pluses: - C++ or SystemC programming What you'll be doing: - ... SystemVerilog, OVM / UVM / or VMM, C++ or SystemC, "verification... more

Sep 05 Intern – ASIC HW Engineer InterDigital King of Prussia, PA

methodology including RTL (VHDL, Verilog, SystemC), simulation, synthesis, etc. Job ... including RTL (VHDL, Verilog, SystemC), simulation, synthesis, etc. · Pragmatic... more

Sep 04 Sr Staff Design Verification Engineer Broadcom San Jose, CA

languages (Verilog/SystemVerilog/SystemC/VHDL), high level languages (C++), ... in languages such as Systemverilog, SystemC, C/C++, Perl, TCL/TK. * Strong... more

Sep 03 Senior Member Technical Staff Mentor Graphics Incorporation Indiana

2-6 years, preferably in implementing bus protocol BFMs or similar. Knowledge of C/C++ and exposure to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of... more

Sep 03 Senior Member Technical Staff Mentor Graphics Indiana

2-6 years, preferably in implementing bus protocol BFMs or similar. Knowledge of C/C++ and exposure to verification environments (SV OVM, SystemC, Vera) is a plus. Knowledge of... more

Sep 02 Graduate Design Engineer - Implementation Artisan Austin, TX

models (TLMs) in a SystemC-based framework •Specification and creation of test harnesses and methodologies using interpreted languages like Python and Perl Verification • Formal... more

Aug 31 Product Engineering SW Architect - Semi and System Software Wipro Technologies Portland, OR

Embedded SW, C++, SystemC/ TLM2/ Perl/ Python/ Basic Architecture concepts, SW processes?Basic ISA modeling / IP Modeling / Writing Tests / AutomationSOC Modeling ( Func / Cycle... more

Aug 29 Senior Computer Architect / Computer Engineer Job Leidos San Diego, CA

8+ years of experience with Verilog, VHDL, SystemC, and/or SystemVerilog for the ... •Platform exploration (SystemC/TLM) for custom SoC using industry standard tools... more

Aug 25 Engineering Lead - Contro.. UTC Aerospace Systems Windsor Locks, CT

and analysis using languages such as SystemC or UML, software requirements modeling and simulation-based verification, HIL and SIL verification testing, network performance... more

Aug 25 ASIC Engineer 3 Juniper Networks Sunnyvale, CA

experience. · Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills. · Must have good leadership/communication skills. · Networking experience is highly... more

Aug 20 MTS ASIC/ Layout Design Engineer AMD Massachusetts

SV/VMM, SV, C++, SystemC, Vera, E)
• Mastery of a scripting language (Shell, Perl, Python, Ruby)
• Verification functional coverage using industry standard coverage analysis... more

Aug 19 Terminal Manager Philadelphia, PA

Quality Management Systemc)       Review delivery schedule to ensure customers requirements are met.d)      Responsible for the training and professional development of assigned... more

Aug 13 MTS ASIC/ Layout Design Engineer Amd | Seamicro Massachusetts

acceptable SV/VMM, SV, C++, SystemC, Vera, E) • Mastery of a scripting language (Shell, Perl, Python, Ruby) • Verification functional coverage using industry standard coverage... more

Aug 05 System Modelling E-solutions Portland, OR

and validating cycle-accurate IP models in SystemC/TLM 1. Integrate IP models in SOC ... infrastructure and peripheral IPs in SystemC · Experience in building virtual... more

Aug 04 Design Modeling Engineer Calsoftlabs-an Alten Group Company San Diego, CA

for implementing and supporting C++ and SystemC functional modelsfor the Digital ... -Design and verification environment at SystemC level -HW/SW co-verification -HLS... more

Jul 29 Master- or Bachelor thesis (f/m) in Engineering and Supply Chain IT - Adaptive SystemC based simulation engine Intel Nuremberg, PA

Engineering and Supply Chain IT - Adaptive SystemC based simulation engine. This ... itself. Content of the thesis is: Adaptive SystemC based simulation engine: -... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of Science degree in Electrical or Computer Engineering with a minimum 9 years of relevant experience or 7... more

Jul 10 Analog EDA Application Engineer Texas Instrutments Dallas, TX

MATLAB, Verilog, Verilog-A,, Verilog-AMS, VHDL, VHDL-AMS and/or SystemC). * Ability to setup and debug analog and mixed-signal simulations and analyze data in Analog Artist is... more

Jul 10 Instant Closure Need Pre-Silicon Engineer @ Simplion Technologies Milpitas, CA

PCIe, USB, SATA, MIPI etc ) or Memory Interfaces ( Flash, DDR, SDIO etc ) or SoC infrastructure blocks ( Bus Infrastructure, DMA etc ). Experience in emulation / systemc is a... more

Jun 10 Licensed Medical Social Worker CHRISTUS Continuing Care Houston, TX

nd policy development.• Experience dealing with difficult or delicate patrons.B. Experience• Experience with Concourse by Book SystemC. Licenses, Registrations, or... more

Jun 09 Senior Principal Analog Design Engineer Terran Systems San Jose, CA

with analog behavioral modeling a plus (SystemC, System Verilog, Matlab) ? Self driven, results -oriented individual capabile of working well with a very experienced and proven... more

Jun 05 Engineer Circuit Design 4 Northrop Grumman Manhattan Beach, CA

and modeling using C/C++, SystemVerilog, or SystemC. EGPD2014Basic Qualifications: Bachelors of Science degree in Electrical or Computer Engineering with a minimum 9 years of... more

May 29 Analog IC Engineer Cybercoders Irvine, CA

- Behavioral modeling with System Verilog, SystemC, Matlab and other languages - Worked in ... - Low power design - A / D Converters - SystemC - System Verilog - PLL - Matlab - High... more

May 26 Electrical Engineer - Consumer Electronics Survios Los Angeles, CA

experience with design verification using SystemC, SystemVerilog or similarExperience with verification and debugging tools such oscilloscope, multimeter, signal and spectrum... more

May 12 ASSOCIATE ASIC/FPGA Verification Engineer L-3 Camden, NJ

proficiency in C/C++, VHDL. Proficiency with SystemC, System Verilog a big plus. Knowledge of UVM desired but not required. Knowledge of high-speed peripheral interfaces... more

Apr 28 Pre- Silicon Verification-(252689) Compnova Santa Clara, CA

• Expertise in c/c++ and systemC. Knowledge of Specman/e a plus. • Knowledge of emulation and writing testbenches for emulation a plus. Excellent communication and team work... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

ec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC, Scripting language Tools:... more

Jan 29 Principal R&D Application Engineer Cadence Design Systems San Jose, CA

programming and system simulation using SystemC is a plus * Must have excellent written and verbal communication skills as well as good problem solving skills. * Able to travel... more

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