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Nov 27 Junior FPGA Engineer Request Technology-robyn Honquest Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Nov 26 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Nov 25 Engineer Circuit Design 3(14015703) Northrop Grumman Manhattan Beach, CA

constrained random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Northrop Grumman... more

Nov 25 Senior Verification Design Automation Engineer Encore Semi San Diego, CA

Verification Languages (OO-HVLs) such as SystemVerilog or VERA, as well as industry standard hardware description languages (HDLs) like Verilog/VHDL. • Experience in industry... more

Nov 25 Digital IC Design Engineer Career Broker Colorado Springs, CO

areas:• RTL design in Verilog and SystemVerilog.• Architecture specification including familiarity with microprocessor and SoC architectures.• Validation of software and hardware... more

Nov 25 Graphics Design Verification Engineer Apple Austin, TX

hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators ... Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman... more

Nov 24 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Nov 24 Design Verification Engineers Collabera San Diego, CA

the design and assertion languages: RTL, SystemVerilog, SystemVerilog Assertions (SVA), VHDL, Verilog, etc. * Verification Methodologies like UVM and Power Aware verification with... more

Nov 24 Senior ASIC Verification Engineer Marvell Santa Clara, CA

enviornment using c/c++ and verilog/systemverilog/uvm. *FPGA prototyping. *good debug skills. *highly motivated to find design issues thru working hard to be a subject/feature... more

Nov 22 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,0 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Nov 21 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Nov 21 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Chicago, IL

Hunter Bond FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Nov 21 DDR PHY IP Logic Designer QUALCOMM Raleigh, NC

timing, running formal, incorporating SystemVerilog assertions. The individual will be responsible for micro-architecture documentation, coding training algorithms, registers, DFT... more

Nov 19 Design Verification Engineer Intelliswift Software Mountain View, CA

verification environment using SystemVerilog and UVM. Identify and write all ... holes and to show progress towards tape-out. systemverilog, uvm, design... more

Nov 17 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Nov 14 Digital Ic Design Engineer Career Development Partners Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Nov 13 Principal Verification Engineer - VEAS06 Cavium San Jose, CA

Requirements: Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification... more

Nov 13 Sr. ASIC Design Engineer (7 years exp. min.) Real Staffing Sunnyvale, CA

logic and processor cores in Verilog and SystemVerilog. Synthesize and optimize RTL ... logic design and VLSI design. Knowledge of SystemVerilog, Verilog and Perl. Ability to... more

Nov 11 Associate Rotation Engineer - MED Mentor Graphics Incorporation Fremont, CA

or FPGA prototyping a plus. Knowledge of SystemVerilog a plus. Excellent verbal and written communication skills in English, self-motivated and results-oriented. International... more

Nov 11 Engineer, Sr Principal - IC Design Verification Broadcom San Jose, CA

level. • Experience using SystemVerilog, VMM or UVM. • Familiar with System Verilog Assertions. • Strong experience in ASIC design verification flows and DV methodologies. •... more

Nov 09 Design Verification Engineer (NCG) Altera San Jose, CA

top and IP level design/verification using SystemVerilog/UVM. You are expected to generate UVM/SV code to match design behavior. Other new methods of verification will also be... more

Nov 09 Verification Engineer II Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Nov 07 Senior ASIC/SOC Design Engineer Evo Portland, OR

tasks SKILLS and REQUIREMENTS Familiar with SystemVerilog for writing testbench and tests Must have either a BS or MS in Electrical Engineering, Computer Engineering or Electrical... more

Nov 06 Staff Design Verification Engineers Commnexus Santa Clara, CA

SystemC modeling, PCI-Express and SystemVerilog. Employer will accept Bachelor’s or foreign equivalent degree and 5 years of experience in integrated chip design verification... more

Nov 06 Logic Design Engineer Results Center Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Nov 04 Logic Design Engineer Marvell Technology Group Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Nov 04 Junior FPGA Engineer Parallel Partners Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Oct 21 FPGA Verification Engineer Job Micron Milpitas, CA

developing Re-Usable Test Benches in SystemVerilog Desired Skills: - Experience with ARM processors verification. - Experience with ARM emulators. - Knowledge of SAS/SATA... more

Oct 08 ASCI Engineer Enterprise Solutions Mountain View, CA

Verilog with OVM experience JD: Expertise in SystemVerilog and OVM methodology. Expertise in Client s internal OVM/Saola infrastructure a plus. Knowledge of stimulus generation... more

Oct 06 IC Verification Engineer Fusion408 Santa Clara, CA

Engineer who is well versed with SystemVerilog, OVM, and C++. This is a highly ... -UVM -BFM What you will be doing. * Utilize SystemVerilog experience in a C++ environment... more

Oct 02 Digital IC Design Engineer Cameron Craig Group Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 24 FPGA Verification Contractor Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Sep 17 Postdoctoral Scholar Pennsylvania State University Pennsylvania

C/C++/C#/Java; Python; ROS; Verilog or SystemVerilog; VHDL; Open CV and Open CL; and Linux. Candidate selected may be subject to a government security investigation. This is a one... more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 04 Senior MTS Design Verification Engineer Amd | Seamicro Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling skills. Working knowledge of a logic synthesis tool such as Synopsys Design Compiler or Cadence RTL... more

Sep 03 Senior MTS Design Verification Engineer AMD Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Aug 20 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: • RTL Coding (Verilog/SystemVerilog) • Micro-Architecture • ... • SystemVerilog (UVM) • STA • AXI Bachelors degree in Electrical Engineering or... more

Mar 24 Design Verification Engineer Google Mountain View, CA

functional verification using SystemVerilog Preferred qualifications: * ... such as PCIe, Ethernet, DDR3/4 * Strong SystemVerilog coding skills. * Excellent... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

experience in verification using OVM/UVM/SystemVerilog o Advanced verification methodologies using constrained random, assertion based verification o Experience in putting... more

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