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Oct 31 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,0 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

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Oct 31 Digital Ic Design Engineer Career Development Partners Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Oct 31 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 29 ASIC Verification Engineer (RTL) HCL America Folsom, CA

Improve coverage and write coverpoints. SystemVerilog, OVM andor UVM experience is a ... pre-silicon validation. rtl system memory verification verilog systemverilog... more

Oct 29 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 29 Junior FPGA Engineer Next Step Systems Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Oct 28 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION (3 Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Oct 28 Staff Design Engineer Encore Semi San Diego, CA

Verification Languages (HVL) such as SystemVerilog to implement tests for complex SOC designs. Execute design verification tasks to meet functional & constrained random coverage... more

Oct 27 Sr. ASIC Verification Engineer Brocade San Jose, CA

sophisticated testbench components in SystemVerilog with UVM and C/C++ Generate ... in the verification of chip designs using SystemVerilog and either UVM or OVM/VMM... more

Oct 27 Verification Design Automation Engineer Collabera San Diego, CA

Verification Languages (OO-HVLs) such as SystemVerilog or VERA, as well as industry standard hardware description languages (HDLs) like Verilog/VHDL Experience in industry... more

Oct 25 Verification Engineer Mindlance San Diego, CA

2. A solid working knowledge of Verilog, SystemVerilog, and UVM. 3. A working knowledge of the Cadence AMS environment would be helpful. **Education:** Required: Bachelor's,... more

Oct 24 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Oct 23 Sr. CAD Engineer Low Power Design Verification Apple Austin, TX

is needed. * Must be fluent in Verilog and SystemVerilog. * Scripting abilities in PERL, TCL or Python is a plus. * Knowledge of C or C++ is a plus. * Experience writing or... more

Oct 22 Emulation/FV Applications Engineer Mentor Graphics Austin, TX

- knowledge of SystemVerilog/Verilog/VHDL language, RTL, behavioral coding and general ASIC debug. • C programming desirable. SystemC and C++ used in conjunction with chip design... more

Oct 22 Emulation/FV Applications Engineer Mentor Graphics Incorporation Austin, TX

- knowledge of SystemVerilog/Verilog/VHDL language, RTL, behavioral coding and general ASIC debug. • C programming desirable. SystemC and C++ used in conjunction with chip design... more

Oct 21 FPGA Verification Engineer Job Micron Milpitas, CA

developing Re-Usable Test Benches in SystemVerilog Desired Skills: - Experience with ARM processors verification. - Experience with ARM emulators. - Knowledge of SAS/SATA... more

Oct 21 Design Verification Engineer Cirrus Logic Austin, TX

SystemVerilog/OVM, UVM, AVM, Vera, e) required. The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog... more

Oct 13 Pre-Si Verification Engineer Intel Israel, PR

using automated tools - mainly Specman or SystemVerilog. - Develop SOC verification ... - Knowledge of the 'e' (Specman) or SystemVerilog and Verilog languages - Clear... more

Oct 10 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Chicago, IL

Hunter Bond FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Oct 08 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage Implementation ... implementing, debugging, and closing SystemVerilog functional coverage groups. more

Oct 06 IC Verification Engineer Fusion408 Santa Clara, CA

Engineer who is well versed with SystemVerilog, OVM, and C++. This is a highly ... -UVM -BFM What you will be doing. * Utilize SystemVerilog experience in a C++ environment... more

Oct 03 Applications Engineer - Verification Tabula Santa Clara, CA

3+ years of industry experience Verilog/SystemVerilog coding experience UVM/OVM Assertion-based verification Creation of verification environments that implement constrained... more

Oct 01 CPU Verification Lead Engineer Broadcom Santa Clara, CA

high level verification language is a must, SystemVerilog is preferred - Well organized, methodical, and detail oriented - Good communication skills and willingness to work in a... more

Sep 24 FPGA Verification Contractor Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Sep 21 Digital Design Verification Engineer Texas Instruments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Sep 17 Postdoctoral Scholar Pennsylvania State University Pennsylvania

C/C++/C#/Java; Python; ROS; Verilog or SystemVerilog; VHDL; Open CV and Open CL; and Linux. Candidate selected may be subject to a government security investigation. This is a one... more

Sep 17 Engineer, Verification Design Results Center Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Sep 16 Engineer, Verification Design Marvell Technology Group Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 04 Jr. Hardware Engineer Eagle Technical Staffing Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Sep 04 Senior MTS Design Verification Engineer Amd | Seamicro Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Senior MTS Design Verification Engineer AMD Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling skills. Working knowledge of a logic synthesis tool such as Synopsys Design Compiler or Cadence RTL... more

Aug 21 Mbr Engrg Staff Lockheed Martin Moorestown, NJ

techniques, including knowledge of SystemVerilog and OVM/UVM. Experience in, or knowledge of, hardware/firmware simulation tools. Experience in, or knowledge of, firmware designs... more

Aug 20 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: • RTL Coding (Verilog/SystemVerilog) • Micro-Architecture • ... • SystemVerilog (UVM) • STA • AXI Bachelors degree in Electrical Engineering or... more

May 30 Engineer, Senior Verification Design Marvell Santa Clara, CA

environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high speed serial... more

Mar 24 Video Codec Design Engineer Google Mountain View, CA

at the Register Transfer Level (RTL) using SystemVerilog as well as synthesis and timing closure of digital designs. * Scripting capability in languages such as perl or python as... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

SICs Knowledge of video codec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC,... more

Feb 21 Verification Engineer Altera San Jose, CA

You will write test plans and implement SystemVerilog/UVM based verification ... with coverage driven verification using SystemVerilog test bench development using... more

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