SOCcentral Jobs
Posted Job Title Company Location

Looking to hire? Post your job today!

More Job Postings from the Web
Nov 06 PMTS - SoC Verification Engineer AMD Boxborough, MA

upon C/C++, SystemC, Vera, Specman, or SystemVerilog required. Requires an understanding of computer architecture and/or graphics. Excellent communication and technical leadership... more

Nov 06 Principle FPGA Designer Saic - McLean Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog performing design trade-offs ... for verification of modules using SystemVerilog, creating and maintaining... more

Nov 06 Senior FPGA Designer Saic - McLean Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more

Nov 06 ASIC Verification Intern Innovative LOGIC Santa Clara, CA

All the work will be done in systemverilog ... You must have good understanding of systemverilog along with verification flow and use of verification tools such as Modelsim. more

Nov 06 Senior ASIC Verification Engineer Innovative LOGIC Santa Clara, CA

DDR3, SATA or SAS. You must be expert in Systemverilog OVM methodology too. Expertise in verilog, System Verilog OVM Good experience in perl, C/C++ Expert in directed testing Good... more

Nov 05 Sr. Verification Engineer Sun Microsystems Santa Clara, CA

designs. - Experienced in Verilog. VERA and SystemVerilog knowledge a plus. - Experience in developing and executing DFT verification test plans and test matrix. - Experience in... more

Nov 04 PMTS - SoC Verification Engineer AMD Boxborough, MA

upon C/C++, SystemC, Vera, Specman, or SystemVerilog required. Requires an understanding of computer architecture and/or graphics. Excellent communication and technical leadership... more

Nov 04 Engineer, Principal Software Developemnt (GPS / Windows CE) Broadcom Santa Clara, CA

for ARM-based SoCs. Experience with SystemVerilog and/or SystemC is highly desirable. Experience debugging in RTL verification environment using waveform viewers such as... more

Nov 04 Sr. Staff IC Verification Engineer Broadcom San Diego, CA

with Verilog, Verilog PLI, SystemVerilog or Vera, UNIX Scripts, C, Perl, Tcl. -Experience with the following areas in design and verification is a plus: Systems with Embedded ARM... more

Nov 04 Sr. Principal Verification Engineer Broadcom Irvine, CA

Specman and/or SystemVerilog) o Develop Test plans from design specifications and Standards documentations o Implement test cases outlined in test plans o Provide test audit... more

Nov 03 FPGA Design Engineer Multiply Levels Active TS SCI Full Scope Polygraph Design Staffing Laurel, MD

of DSP Algorithms -- Matlab experience -- SystemVerilog experience -- Embedded Hardware -Software design -- FPGA design and implementation on wireless communication signal... more

Nov 02 Engineer, Senior Design Marvell Technology Group Santa Clara, CA

of the above designs using SystemVerilog randomized simulation. Define coverage metrics to quantify the simulation results. Synthesis and post-layout timing closure for the above... more

Nov 02 Sr. Staff IC Verification Engineer Broadcom San Diego, CA

with Verilog, Verilog PLI, SystemVerilog or Vera, UNIX Scripts, C, Perl, Tcl. -Experience with the following areas in design and verification is a plus: Systems with Embedded ARM... more

Nov 01 Engineer, Senior Design Marvell Santa Clara, CA

circuit design a plus. Experience with SystemVerilog for verification a plus. ... Verification of the above designs using SystemVerilog randomized simulation. Define... more

Nov 01 EDA Verification Engineer, Senior QUALCOMM San Diego, CA

Strong knowledge of HVLs(VERA), HDLs(Verilog/VHDL/SystemVerilog), C/C++/SystemC. RTL simulation (ModelSim, VCS, Vera), Formal verification techniques (e.g. Model checking,... more

Nov 01 Hardware Design Verification Engineer - Modem Communications QUALCOMM San Diego, CA

Strong working knowledge of HVLs: SystemVerilog TB, VERA, or e-Specman * Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Education Requirements Required: Bachelor's, Computer... more

Nov 01 Director/Principal Engineer of Design Verification and Validation - Wireless Communications QUALCOMM San Diego, CA

Experience with directed random verification in SystemVerilog, Vera, Verisity/Specman and/or SystemC preferred. You should have experience leading dynamic, effective teams and as... more

Oct 31 Sr. Principal Verification Engineer Broadcom Irvine, CA

Specman and/or SystemVerilog)o Develop Test plans from design specifications and Standards documentationso Implement test cases outlined in test planso Provide test audit report... more

Oct 31 RTL Design and Verification Engineer ES/LS HW, R&D Tyco Healthcare Boulder, CO

scripting (Perl, python, Tcl, shell), SystemVerilog, and C/C++ experience required. . VHDL experience is a plus. OVM experience is a strong plus. . Experience with SVA,... more

Oct 30 ASIC Logic Design and Verification Engineer (Raleigh QUALCOMM Cary, NC

experience with coding RTL [SystemVerilog (preferred), Verilog or VHDL] ... testbenches in HVL [Vera (preferred), SystemVerilog TestBench or e]. Additional... more

Oct 30 Senior FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more

Oct 30 Principal FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog performing design trade-offs ... for verification of modules using SystemVerilog, creating and maintaining... more

Oct 30 Senior FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more

Oct 30 Principal FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog performing design trade-offs ... for verification of modules using SystemVerilog, creating and maintaining... more

Oct 30 Sr. Verification Engineer Sun Microsystems Santa Clara, CA

Experienced in Verilog. VERA and SystemVerilog knowledge a plus. - Experience in developing and executing DFT verification test plans and test matrix. - Experience in developing... more

Oct 29 Sr. Verification Engineer Sun Microsystems Santa Clara, CA

designs. - Experienced in Verilog. VERA and SystemVerilog knowledge a plus. - Experience in developing and executing DFT verification test plans and test matrix. - Experience in... more

Oct 28 NRE - Design Verification Engineer AMD Boxborough, MA

in C/C++ - Experience in Verilog/SystemVerilog - Experience working with Synopsys VCS and waveform viewers - Working knowledge of UNIX/Linux operating systems and debug... more

Oct 28 Design Verification Engineer Stec San Diego, CA

Verilog/VHDL, SystemC, SystemVerilog, OVM - C/C++, Matlab, scripting languages - 2-3 years Experience with OVM or URM methodology - Additional experience in these area are a... more

Oct 23 ASIC Logic Design and Verification Engineer (Raleigh QUALCOMM Cary, NC

Significant experience with coding RTL [SystemVerilog (preferred), Verilog or VHDL] ... testbenches in HVL [Vera (preferred), SystemVerilog TestBench or e]. Additional... more

Oct 23 Principal FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog performing design trade-offs ... for verification of modules using SystemVerilog, creating and maintaining... more

Oct 23 Applications Engineer Manager - Emulation Mentor Graphics San Jose, CA

or verification experience - Knowledge of SystemVerilog/Verilog/VHDL language, RTL, behavioral coding and general ASIC debug. - Must have previous experience with industry... more

Oct 23 Senior Verification Engineer SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and support of test engineers during chip bring-up. This position requires a Bachelors degree in Electrical Engineering,... more

Oct 23 Applications Engineer Manager - Emulation Mentor Graphics San Jose, CA

or verification experience - Knowledge of SystemVerilog/Verilog/VHDL language, RTL, behavioral coding and general ASIC debug. - Must have previous experience with industry... more

Oct 22 Senior Verification Engineer SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and support of test engineers during chip bring-up. This position requires a Bachelors degree in Electrical Engineering,... more

Oct 22 Technical Leader , Advanced Verification Technologies Cadence Design San Diego, CA

utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.Experience: 7+ years as... more

Oct 22 Sr. Principal Verification Engineer Broadcom Irvine, CA

Specman and/or SystemVerilog)o Develop Test plans from design specifications and Standards documentationso Implement test cases outlined in test planso Provide test audit report... more

Oct 21 Technical Leader , Advanced Verification Technologies Cadence Design San Diego, CA

utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required. Experience: 7+ years... more

Oct 20 FPGA Design Engineer Active Top Secret SCI Lifestyle Poly Design Staffing Columbia, MD

of DSP Algorithms'Matlab experience'SystemVerilog experience'Embedded Hardware Software design'FPGA design and implementation on wireless communication signal processing systems... more

Oct 20 Senior FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more

Oct 20 Principle FPGA Designer (m) SAIC Columbia, MD

designs in Altera Stratix IV FPGAs using SystemVerilog performing design trade-offs ... for verification of modules using SystemVerilog, creating and maintaining... more

Oct 20 RTL Design and Verification Engineer ES/LS HW, R&D Covidien Boulder, CO

scripting (Perl, python, Tcl, shell), SystemVerilog, and C/C++ experience required. VHDL experience is a plus. OVM experience is a strong plus. Experience with SVA, covergroups,... more

Oct 20 Senior Verification Engineer SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and support of test engineers during chip bring-up. This position requires a Bachelors degree in Electrical Engineering,... more

Oct 20 RTL Design and Verification Engineer ES/LS HW, R&D Tyco Healthcare Boulder, CO

scripting (Perl, python, Tcl, shell), SystemVerilog, and C/C++ experience required. . VHDL experience is a plus. OVM experience is a strong plus. . Experience with SVA,... more

Oct 19 Sr. Verification Engineer SanDisk Milpitas, CA

responsibilities will include support of SystemVerilog Assertions and behavioral ... This position also requires experience of SystemVerilog TestBench development and... more

Oct 19 Digital Design Staff Engineer STMicroelectronics Santa Clara, CA

Experience Hardware modeling in C/SystemC or HDVL language (SystemVerilog, Specman). VLSI systems design and verification techniques. Channel coding algorithms and read/write... more

Oct 17 Engineer, Principal Software Developemnt (GPS / Windows CE) Broadcom Santa Clara, CA

for ARM-based SoCs. Experience with SystemVerilog and/or SystemC is highly desirable. Experience debugging in RTL verification environment using waveform viewers such as... more

Oct 17 Engineer, Principal Software Developemnt (GPS / Windows CE) Broadcom Santa Clara, CA

for ARM-based SoCs. Experience with SystemVerilog and/or SystemC is highly desirable. Experience debugging in RTL verification environment using waveform viewers such as... more

Oct 17 Sr. Verification Engineer SanDisk Milpitas, CA

responsibilities will include support of SystemVerilog Assertions and behavioral ... This position also requires experience of SystemVerilog TestBench development and... more

Oct 16 ASIC Logic Design and Verification Engineer (Raleigh QUALCOMM Cary, NC

Significant experience with coding RTL [SystemVerilog (preferred), Verilog or VHDL] ... testbenches in HVL [Vera (preferred), SystemVerilog TestBench or e]. Excellent... more

Oct 16 ASIC Logic Design and Verification Engineer (Raleigh QUALCOMM Cary, NC

Significant experience with coding RTL [SystemVerilog (preferred), Verilog or VHDL] ... testbenches in HVL [Vera (preferred), SystemVerilog TestBench or e]. Additional... more