Design Verification Engineer - ASIC - Large Scale systems - C/C++ - Vera - SystemVerilog - Test Plan near New York City, NY This job is open as of 2/7/2010. Apply Now! Not a fit... more

tools and languages such as Verilog, VHDL, SystemVerilog, OVA, especially SystemC and so forth. The applicant must understand the importance of performance tuning and... more

gineering is preferred. ? At least seven years of ASIC verification experience ? Solid understanding of C, hdl, Verilog, C++, & SystemC ? SystemVerilog knowledge is plus ?... more

verification (FPGA/ASIC) Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills Experience with several scripting languages (e.g. Perl, Bash, etc.) Solid... more

Development team - Develop and maintain OVM SystemVerilog and e libraries- Innovate new ... focus would be lead developer for OVM SystemVerilog- Requires collaborating in... more

qualifications include: - Expertise in SystemVerilog*, and Perl coding - Expertise in simulation and debug using VCS* - Strong familiarity with logic design and verification... more

* Experience with SystemVerilog and/or SystemC is highly desirable. * Experience debugging in RTL verification environment using waveform viewers such as Debussy, NCverilog or VCS... more

applications * Proficiency with vhdl and SystemVerilog * Proficiency with a full simulator like ModelSim * Familiarity with Secure IP and experience evaluating vendor IP cores a... more

logic design using VHDL/Verilog/SystemVerilog; synthesis, timing, and net list generation using industry standard EDA tools; design verification using Mentor Graphics ModelSim;... more

products and circuits.- Expertise with SystemVerilog, functional coverage, and assertions is highly desired- Experience with successful tape out of mixed-signal products from... more

verification (FPGA/ASIC) * Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills * Experience with several scripting languages (e.g. Perl, Bash, etc.) *... more

include the following: * Logic design using SystemVerilog * Design verification using ... operating systems * Logic design skills: SystemVerilog and VHDL * Verification... more

proficient in HDL ? VHDL, Verilog, and SystemVerilog, SDC - Timing Constraint language, and Tcl - scripting and database access. The candidate needs to have experience with... more

developing and maintaining state-of-the-art SystemVerilog OVM-based testbench ... issues. Responsibilities Create OVM-based SystemVerilog testbench components and test... more

utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required. Experience: 7+ years... more

components (monitors, BFM's etc.) in SystemVerilog with a thorough understanding of the functionality and performance of the blocks, and augmenting proven internal/external... more

utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.Experience: 7+ years as... more

verification (FPGA/ASIC) * Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills * Experience with several scripting languages (e.g. Perl, Bash, etc.) *... more

in multiple design languages including SystemVerilog, VHDL, and SystemC. To find out more about Mentor Graphics Corporation, please see www.mentor.com. We are looking for entry... more

with Synopsys tools, Design Compiler, SystemVerilog/VCS, Primetime, and DFT Compiler is a strong plus. - Good working knowledge of scripting and Perl/Tcl. - Good communication... more