SystemVerilog jobs
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| Feb 09 | Platforms Storage FPGA/ASIC Design Infrastructure Engineer | Mountain View, CA | |
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verification (FPGA/ASIC) Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills Experience with several scripting languages (e.g. Perl, Bash, etc.) Solid... more |
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| Feb 08 | Design Verification Engineer - ASIC - Large Scale systems - C/C++ - Vera - SystemVerilog - Test Plan | Cybercoders | New York, NY |
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Design Verification Engineer - ASIC - Large Scale systems - C/C++ - Vera - SystemVerilog - Test Plan near New York City, NY This job is open as of 2/7/2010. Apply Now! Not a fit... more |
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| Feb 08 | Digital Verification Engineer | Fusion408 | San Jose, CA |
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of C, hdl, Verilog, C++, & SystemC ? SystemVerilog knowledge is plus ? Previous experience working with DSP verification is another plus. ? Basic understanding of shell scripting... more |
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| Feb 08 | Sr. Staff R&D Engineer | Synopsys | Mountain View, CA |
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tools and languages such as Verilog, VHDL, SystemVerilog, OVA, especially SystemC and so forth. The applicant must understand the importance of performance tuning and... more |
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| Feb 07 | Design Verification Engineer - ASIC - Large Scale systems | Cybercoders | New York, NY |
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Testing, Model Checking, C/C++, C++. Vera, SystemVerilog, First-Pass, Silicon Success, ... ASIC - Large Scale systems - C/C++ - Vera - SystemVerilog - Test Plan If you are a... more |
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| Feb 07 | Digital Verification Engineer | Fusion408 | San Jose, CA |
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gineering is preferred. ? At least seven years of ASIC verification experience ? Solid understanding of C, hdl, Verilog, C++, & SystemC ? SystemVerilog knowledge is plus ?... more |
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| Feb 06 | Verification Engineer | AMD | Boxborough, MA |
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/MS in EE, CS, CSE - Experience with Verilog and C/C++ required - Background and interest in computer graphics a strong plus - Experience with SystemVerilog, OVM, perl, test APIs... more |
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| Feb 06 | Platforms Storage FPGA/ASIC Design Infrastructure Engineer | Mountain View, CA | |
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verification (FPGA/ASIC) Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills Experience with several scripting languages (e.g. Perl, Bash, etc.) Solid... more |
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| Feb 05 | Senior FPGA Designer (m) | SAIC | Columbia, MD |
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designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more |
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| Feb 04 | Staff Solutions Engineer, OVM Specialist | Cadence Design Systems | San Jose, CA |
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Development team - Develop and maintain OVM SystemVerilog and e libraries- Innovate new ... focus would be lead developer for OVM SystemVerilog- Requires collaborating in... more |
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| Feb 04 | Intern | Intel | Folsom, CA |
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qualifications include: - Expertise in SystemVerilog*, and Perl coding - Expertise in simulation and debug using VCS* - Strong familiarity with logic design and verification... more |
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| Feb 04 | Intern | Intel | Folsom, CA |
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qualifications include: - Expertise in SystemVerilog*, and Perl coding - Expertise in simulation and debug using VCS* - Strong familiarity with logic design and verification... more |
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| Feb 04 | Platforms Storage FPGA/ASIC Design Infrastructure Engineer | Mountain View, CA | |
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verification (FPGA/ASIC) Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills Experience with several scripting languages (e.g. Perl, Bash, etc.) Solid... more |
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| Feb 03 | Engineer, Principal Software Developemnt (GPS / Windows CE) | Broadcom | Santa Clara, CA |
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* Experience with SystemVerilog and/or SystemC is highly desirable. * Experience debugging in RTL verification environment using waveform viewers such as Debussy, NCverilog or VCS... more |
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| Feb 03 | Senior FPGA Designer (m) | Saic - McLean | Columbia, MD |
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designs in Altera Stratix IV FPGAs using SystemVerilog and performing trade-offs to ... verification of design modules using SystemVerilog, creating and maintaining... more |
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| Feb 03 | FPGA Engineer at Chicago Trading Firm | Chicago, IL | |
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applications * Proficiency with vhdl and SystemVerilog * Proficiency with a full simulator like ModelSim * Familiarity with Secure IP and experience evaluating vendor IP cores a... more |
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| Feb 02 | ASIC HDC SAS and SATA Development Engineer - 2952 | Hitachi Global Storage Technologies | California |
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include the following: * Logic design using SystemVerilog * Design verification using ... operating systems * Logic design skills: SystemVerilog and VHDL * Verification... more |
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| Feb 02 | Controller Development Engineer - 2852 | Hitachi Global Storage Technologies | Minnesota |
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logic design using VHDL/Verilog/SystemVerilog; synthesis, timing, and net list generation using industry standard EDA tools; design verification using Mentor Graphics ModelSim;... more |
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| Feb 02 | Preamp Verification Engineer | LSI | Mendota Heights, MN |
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products and circuits. - Expertise with SystemVerilog, functional coverage, and assertions is highly desired - Experience with successful tape out of mixed-signal products from... more |
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| Feb 02 | Preamp Verification Engineer | LSI | St Paul, MN |
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products and circuits.- Expertise with SystemVerilog, functional coverage, and assertions is highly desired- Experience with successful tape out of mixed-signal products from... more |
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| Feb 02 | Hardware Design Verification Engineer - Modem Communications | QUALCOMM | San Diego, CA |
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testing Strong working knowledge of HVLs: SystemVerilog TB, VERA, or e-Specman Verilog or VHDL, C/C++, Tcl/Perl/shell-scriptingAdditional SkillsEducation RequirementsRequired:... more |
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| Feb 01 | Platforms Storage FPGA/ASIC Design Infrastructure Engineer | Mountain View, CA | |
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verification (FPGA/ASIC) * Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills * Experience with several scripting languages (e.g. Perl, Bash, etc.) *... more |
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| Jan 31 | Principal IC Design Engineer | Broadcom | Irvine, CA |
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skills* high level verification tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation* DSP function hardware... more |
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| Jan 31 | ASIC HDC SAS and SATA Development E... | Hitachi Global Storage | San Jose, CA |
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include the following: * Logic design using SystemVerilog * Design verification using ... operating systems * Logic design skills: SystemVerilog and VHDL * Verification... more |
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| Jan 29 | Senior Verification Engineer | Denali Software | Austin, TX |
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developing and maintaining state-of-the-art SystemVerilog OVM-based testbench ... issues. ResponsibilitiesCreate OVM-based SystemVerilog testbench components and test... more |
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| Jan 29 | SR Staff Product Applications Engineer* | Xilinx | Longmont, CO |
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proficient in HDL ? VHDL, Verilog, and SystemVerilog, SDC - Timing Constraint language, and Tcl - scripting and database access. The candidate needs to have experience with... more |
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| Jan 29 | Principal IC Design Engineer | Broadcom | Irvine, CA |
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skills * high level verification tools like SystemVerilog, System C or Specman is desirable. * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware... more |
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| Jan 28 | Senior Verification Engineer | Denali Software | Austin, TX |
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developing and maintaining state-of-the-art SystemVerilog OVM-based testbench ... issues. Responsibilities Create OVM-based SystemVerilog testbench components and test... more |
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| Jan 27 | Staff Solutions Engineer, OVM Specialist | Cadence Design Systems | San Jose, CA |
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focus would be lead developer for OVM SystemVerilog - Requires collaborating in ... Requirements Must Haves Strong SystemVerilog language expertise Testbench... more |
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| Jan 27 | Sr Sales Technical Leader | Cadence Design Systems | San Diego, CA |
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utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required. Experience: 7+ years... more |
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| Jan 27 | Component Design Engineer | Intel | Phoenix, AZ |
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components (monitors, BFM's etc.) in SystemVerilog with a thorough understanding of the functionality and performance of the blocks, and augmenting proven internal/external... more |
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| Jan 26 | Component Design Engineer | Intel | Phoenix, AZ |
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components (monitors, BFM's etc.) in SystemVerilog with a thorough understanding of the functionality and performance of the blocks, and augmenting proven internal/external... more |
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| Jan 25 | ASIC Design Engineer | Aprconsulting | Richardson, TX |
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(e.g. functional coverage, SystemC, SystemVerilog) * Proficiency using latest ASIC / FPGA simulation tools (e.g. Questasim, ncsim) * Familiarity with revision control concepts and... more |
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| Jan 23 | Sales Technical Leader , Advanced Verification Technologies | Cadence Design Systems | San Diego, CA |
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utilizing e-language tools [SpecMan], Vera, SystemVerilog or SystemC/C++ is required. Track record of successfully verifying complex ASICs is also required.Experience: 7+ years as... more |
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| Jan 23 | Logic Verification Engineer | Intel | Folsom, CA |
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ASIC design flow - Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator - Familiarity with coverage concepts, testplans, testbenches,... more |
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| Jan 22 | Platforms Storage FPGA/ASIC Design Infrastructure Engineer | Mountain View, CA | |
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verification (FPGA/ASIC) * Strong Verilog & SystemVerilog knowledge, Strong RTL design validation skills * Experience with several scripting languages (e.g. Perl, Bash, etc.) *... more |
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| Jan 22 | Software Developent Engineer - DVT | Mentor Graphics | Salem, OR |
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in multiple design languages including SystemVerilog, VHDL, and SystemC. To find out more about Mentor Graphics Corporation, please see www.mentor.com. We are looking for entry... more |
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| Jan 22 | Software Developent Engineer - DVT | Mentor Graphics | Portland, OR |
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in multiple design languages including SystemVerilog, VHDL, and SystemC. To find out more about Mentor Graphics Corporation, please see www.mentor.com. We are looking for entry... more |
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| Jan 22 | Principal IC Design Engineer | Broadcom | Irvine, CA |
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skills high level verification tools like SystemVerilog, System C or Specman is desirable. MATLAB and C/C++ based system simulation and evaluation DSP function hardware... more |
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| Jan 21 | Sr. R&D Engineer | Synopsys | Mountain View, CA |
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with Synopsys tools, Design Compiler, SystemVerilog/VCS, Primetime, and DFT Compiler is a strong plus. - Good working knowledge of scripting and Perl/Tcl. - Good communication... more |
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