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Sep 19 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,0 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

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Sep 20 Design Verification Engineer Asquare.com San Jose, CA

on working experience in verification with SystemVerilog 5 years experience with UVM Experience with requirements tracing US Citizenship Contact (408) 203-6828 verification design... more

Sep 19 Senior Staff Design Engineer Xilinx San Jose, CA

· Expert level understanding of Verilog, SystemVerilog, Timing Constraints and Digital Design principles. · Hands on experience of Front End Design and Implementation steps... more

Sep 19 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Chicago, IL

Hunter Bond FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Sep 19 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Sep 18 Senior Design Verification (Job Nbr 13012607) PDS Tech Santa Clara, CA

experience Verification language: Specman / SystemVerilog / Verilog / VHDL HDL simulators / wave form viewers: NCSIM / ModelSim / VCS / DVE / Verdi Perl, Shell scripting,... more

Sep 17 Engineer, Verification Design Results Center Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Sep 17 Postdoctoral Scholar Pennsylvania State University Pennsylvania

C/C++/C#/Java; Python; ROS; Verilog or SystemVerilog; VHDL; Open CV and Open CL; and Linux. Candidate selected may be subject to a government security investigation. This is a one... more

Sep 16 Graphics Verification Engineer Apple Austin, TX

Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman ... hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Sep 11 FPGA Engineer Job Leidos Columbia, MD

• 2 years of experiences with Verilog (Systemverilog for verification) hardware ... language (including Systemverilog with OVM/UVM) Leidos Overview:Leidos is an applied... more

Sep 11 ASIC RTL Design Engineer Encore Semi San Diego, CA

ing synthesis, simulation, and timing tools. • Use of third party IP cores including microprocessors and peripheral cores. • VHDL experience required, SystemVerilog experience is... more

Sep 11 Engineer, Verification Design Marvell Santa Clara, CA

environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high speed serial... more

Sep 11 Junior FPGA Engineer Ginas Tech Jobs Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Sep 10 Design Verification Engineer (NCG) Altera San Jose, CA

top and IP level design/verification using SystemVerilog/UVM. You are expected to generate UVM/SV code to match design behavior. Other new methods of verification will also be... more

Sep 10 ASIC VERIFICATION INFRASTRUCTURE ENGINEER NVIDIA Santa Clara, CA

graphics and computing chips. The Verilog, SystemVerilog, UVM, C++, and Perl ... - Verification language skills: Verilog, SystemVerilog and UVM preferred - Excellent... more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 09 Engineer, Verification Design Marvell Technology Group Santa Clara, CA

verification environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high... more

Sep 04 Jr. Hardware Engineer Eagle Technical Staffing Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Sep 03 ASIC Verification Engineer - Boise, Idaho Job Micron Longmont, CO

developing Re-Usable Test Benches in SystemVerilog - Additional Skills: - Knowledge of SAS/SATA protocols. It has been and will continue to be the policy of Micron to administer... more

Sep 03 ASIC Design Engineer Footbridge - IT Division Westford, MA

• Experience in ASIC verification using SystemVerilog • Strong problem solving and ASIC debugging skills • Experience in Constrained-random verification is a strong plus •... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling skills. Working knowledge of a logic synthesis tool such as Synopsys Design Compiler or Cadence RTL... more

Sep 03 Senior MTS Design Verification Engineer AMD Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Aug 31 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... • Deep understanding of HVLs: SystemVerilog/OVM/UVM, RTL design experience... more

Aug 22 Digital Design Verification Engineer Texas Instrutments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Aug 20 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: • RTL Coding (Verilog/SystemVerilog) • Micro-Architecture • ... • SystemVerilog (UVM) • STA • AXI Bachelors degree in Electrical Engineering or... more

Aug 20 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Aug 18 Sr Member Eng Stf Lockheed Martin Moorestown, NJ

techniques, including knowledge of SystemVerilog and OVM/UVM. Experience in, or knowledge of, hardware/firmware simulation tools. Experience in, or knowledge of, firmware designs... more

Aug 11 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

languages such as VHDL, Verilog, or SystemVerilog. This position provides an exciting opportunity to lead the development and design of state of the art electronic... more

Aug 05 Design Verification Engineer Mindlance San Jose, CA

ASIC design flows Working experience with SystemVerilog and/or UVM Knowledge of wireless communication and good grasp of DSP fundamentals is desirable. **Education:** Preferred:... more

Aug 05 FPGA Verification Engineer Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Jul 25 Design Verification Engineer Cirrus Logic Austin, TX

SystemVerilog/OVM, UVM, AVM, Vera, e) required. The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog... more

Jul 22 WLAN PHY Digital Design Verification Enginee Huntech Consultants Massachusetts

testbench and reference model code in SystemVerilog, C, and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 09 Sr. Digital Design Engineer Intel Illinois

Desired skills/tools: - DPI-C, SystemVerilog, UVM - VCS, Verdi, Spyglass - ASIC synthesis, formal verification, gate level simulation, static timing analysis, and/or power... more

Jun 05 Engineer Circuit Design 4 Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. EGPD2014Basic... more

May 14 Lead Mixed-Signal Pre-Silicon Functional Verification Engineer (E1922125) QUALCOMM San Diego, CA

Functional Verification, OVM, UVM, SystemVerilog, Audio, CODEC, Digital, Mixed-signal, Analog, Lead You will need to login into your profile to apply for this job. If you are... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage Implementation ... implementing, debugging, and closing SystemVerilog functional coverage groups. more

Mar 24 Design Verification Engineer Google Mountain View, CA

functional verification using SystemVerilog Preferred qualifications: * ... such as PCIe, Ethernet, DDR3/4 * Strong SystemVerilog coding skills. * Excellent... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

SICs Knowledge of video codec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC,... more

Feb 12 Senior MTS Design Verification Engineer Amd | Seamicro Sunnyvale, CA

of industry/internal interfaces with SystemVerilog/ C++ • Excellent debug skills with ability to quickly and accurately root cause failures and make high quality verification... more

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