Posted Job Title Company Location

Looking to hire? Post your job today!

More Job Postings from the Web
Dec 21 Sr. CAD Engineer Low Power Design Verification Apple Austin, TX

is needed. * Must be fluent in Verilog and SystemVerilog. * Scripting abilities in PERL, TCL or Python is a plus. * Knowledge of C or C++ is a plus. * Experience writing or... more

Dec 21 Junior FPGA Engineer Request Technology-stephanie Baker Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Dec 20 Verification Engineer Asquare.com Dallas, TX

on working experience in verification with SystemVerilog Extensive experience with UVM Experience with requirements tracing US Citizenship Contact (408) 203-6828 Verification... more

Dec 20 Verification Design Automation Engineer Collabera California

Verification Languages (OO-HVLs) such as SystemVerilog or VERA, as well as industry standard hardware description languages (HDLs) like Verilog/VHDL Experience in industry... more

Dec 19 R&D Engineer IC Design 3 Avago Technologies Colorado Springs, CO

but not limited to: • RTL Coding (Verilog/SystemVerilog) • Micro-Architecture • ... • SystemVerilog (UVM) • STA • AXI Bachelors degree in Electrical Engineering or... more

Dec 18 Digital Ic Design Engineer Career Development Partners Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Dec 17 Digital IC Design Engineer Systems Technology Intl (sti) Dallas, TX

the company. • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Dec 17 Sr. Engineering Manager – Communications FPGA Rockwell Collins Cedar Rapids, IA

to develop VHDL, Verilog, and SystemVerilog for military communications products based on software defined radio architectures. Candidate will lead the engineering team using... more

Dec 16 FPGA Developer Open Systems Technologies New York City, NY

experience 10+ years experience with Verilog/SystemVerilog/VHDL 2+ years experience with network protocols such as Ethernet/IP/TCP 5+ years experience with C/C++/JAVA/Embedded... more

Dec 16 Senior FPGA Engineer Next Step Systems Chicago, IL

-Expert level proficiency in Verilog and/or SystemVerilog ... FPGA Engineer, FPGA Design, Xilinx, Altera, SystemVerilog, C/C++ Programming, Low... more

Dec 13 Design Verification Engineer Mindlance San Jose, CA

ASIC design flows Working experience with SystemVerilog and/or UVM Knowledge of wireless communication and good grasp of DSP fundamentals is desirable. **Education:** Preferred:... more

Dec 13 Digital Hardware Design Automation Engineer (QCT QUALCOMM Austin, TX

QCT Austin Digital Hardware Design Automation Engineer - This position will help drive new ... industry standard EDA tools * Experience with coding in HDL languages such as... more

Dec 12 Engineer, Principal - IC Design Verification Broadcom Irvine, CA

level. • Experience using SystemVerilog, VMM or UVM. • Familiar with System Verilog Assertions. • Strong experience in ASIC design verification flows and DV methodologies. •... more

Dec 12 Sr. Verification Engineer Cyreq Austin, TX

latest verification methodologies such as SystemVerilog, OVM/UVM Architectures and implementing SoC testbench, developing directed, random, and application use case tests to... more

Dec 11 ASIC Design Verification Engineer Job Yoh Mountain View, CA

- Expertise in developing SystemVerilog / UVM based DV environments, test plans, testbenches, assertions, coverage - Knowledge of scripting languages such as TCL, Perl or Python -... more

Dec 11 Intern, Verification CAD Internal Austin, TX

coding in HDL languages such as Verilog, SystemVerilog, or VHDL * Experience with ... verification methodologies including UVM, SystemVerilog, functional coverage, and... more

Dec 11 Design Verification Engineer Amazon Austin, TX

testing designs using SystemVerilog based UVM or VMM environments * Experience ... * Expert knowledge of SystemVerilog and UVM * Proficient with scripting languages... more

Dec 03 SoC Design and Integration Engineer Novus Resources Raleigh, NC

in Logic Design, VHDL, Verilog & SystemVerilog RTL, verification, synthesis, LINT and static timing analysis, clock domain crossing techniques/implementation and formal... more

Nov 25 Engineer Circuit Design 3(14015703) Northrop Grumman Manhattan Beach, CA

constrained random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Northrop Grumman... more

Nov 24 Senior ASIC Verification Engineer Marvell Santa Clara, CA

enviornment using c/c++ and verilog/systemverilog/uvm. *FPGA prototyping. *good debug skills. *highly motivated to find design issues thru working hard to be a subject/feature... more

Nov 24 Digital Design & Verification Engineer Fusion408 Colorado Springs, CO

& microprocessor * RTL design in Verilog and SystemVerilog. * software and hardware product validation. * Strong experience developing test plans & test benches. The candidate... more

Nov 24 FPGA VERIFICATION ENGINEER - SWITCHING DIVISION Georgia Department of Labor Alpharetta, GA

verification languages is required. SystemVerilog experience is preferred. ... oriented hardware verification languages, SystemVerilog is preferred. Knowledge and... more

Nov 21 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Chicago, IL

Hunter Bond FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Nov 07 Senior ASIC/SOC Design Engineer Evo Portland, OR

tasks SKILLS and REQUIREMENTS Familiar with SystemVerilog for writing testbench and tests Must have either a BS or MS in Electrical Engineering, Computer Engineering or Electrical... more

Nov 05 Functional Verification Engineering Professional IBM Poughkeepsie, NY

programming using languages such as C++ and SystemVerilog, experience in scripting languages such as Perl, working knowledge of Hardware Description Language (HDL) (Very High... more

Oct 29 Digital Design / Verification Engineer(s) Allegro Microsystems Manchester, NH

oriented language is highly desired (C++, SystemVerilog, etc.), as is exposure to one of the structured verification methodologies (VMM, OVM, UVM, etc). Typical tasks for a... more

Oct 21 FPGA Verification Engineer Job Micron Milpitas, CA

developing Re-Usable Test Benches in SystemVerilog Desired Skills: - Experience with ARM processors verification. - Experience with ARM emulators. - Knowledge of SAS/SATA... more

Oct 08 ASCI Engineer Enterprise Solutions Mountain View, CA

Verilog with OVM experience JD: Expertise in SystemVerilog and OVM methodology. Expertise in Client s internal OVM/Saola infrastructure a plus. Knowledge of stimulus generation... more

Oct 08 Pre Silicon consultant in CA/PA Spectraforce Technologies Santa Clara, CA

UVM methodology b. Hands on experience with SystemVerilog c. Hands on experience with Functional coverage d. Ability to develop testplans will be an advantage e. Overall... more

Oct 02 Digital IC Design Engineer Cameron Craig Group Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 24 FPGA Verification Contractor Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Sep 24 Engineer, Senior Verification Design Marvell Technology Group Santa Clara, CA

verification environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 04 Senior MTS Design Verification Engineer Amd | Seamicro Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling skills. Working knowledge of a logic synthesis tool such as Synopsys Design Compiler or Cadence RTL... more

Sep 03 Senior MTS Design Verification Engineer AMD Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Aug 06 Sr Member Eng Stf Lockheed Martin Moorestown, NJ

techniques, including knowledge of SystemVerilog and OVM/UVM. Experience in, or knowledge of, hardware/firmware simulation tools. Experience in, or knowledge of, firmware designs... more

Jul 22 WLAN PHY Digital Design Verification Enginee Huntech Consultants Boxborough, MA

testbench and reference model code in SystemVerilog, C, and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Mar 24 Design Verification Engineer Google Mountain View, CA

functional verification using SystemVerilog Preferred qualifications: * ... such as PCIe, Ethernet, DDR3/4 * Strong SystemVerilog coding skills. * Excellent... more

Jobs by Simply Hired