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Aug 29 FPGA, Verilog, Asic, SystemVerilog - Trading Firm - $200,000 Hunter Bond Chicago, IL

FPGA, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently seeking a ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

More Job Postings from the Web
Sep 01 ASIC RTL Design Engineer Encore Semi San Diego, CA

ing synthesis, simulation, and timing tools. • Use of third party IP cores including microprocessors and peripheral cores. • VHDL experience required, SystemVerilog experience is... more

Sep 01 FPGA Engineer Request Technology-anthony Honquest Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Sep 01 Junior FPGA Engineer Request Technology-stephanie Baker Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Aug 31 Junior FPGA Engineer Next Step Systems Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Aug 31 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... • Deep understanding of HVLs: SystemVerilog/OVM/UVM, RTL design experience... more

Aug 30 Design Verification Engineer Asquare.com San Jose, CA

on working experience in verification with SystemVerilog 5 years experience with UVM Experience with requirements tracing US Citizenship Contact (408) 203-6828 verification design... more

Aug 30 Front End Design Automation Engineer Classifiedads.com Santa Clara, CA

verification, required * Experience in SystemVerilog and Verilog, highly desired * ... plus * Prior experience writing RTL code in SystemVerilog, or experience with Synopsys... more

Aug 29 FPGA, Verilog, Asic, SystemVerilog - Trading Firm - $200,000 Chicago, IL

considered Hunter Bond FPGA, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Aug 28 Senior Design Verification Engineer Analog Devices Norwood, MA

level verification; programming using SystemVerilog or similar hardware verification language; Perl and C++ programming; and, using the Linux operating system. For positions... more

Aug 27 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: RTL Coding (Verilog/SystemVerilog) Micro-Architecture ... Synopsys CVS and SVN Perl Scripting SystemVerilog (UVM) STA DMA Designs AXI... more

Aug 24 Verification Engineers Ee-recruiters Santa Clara, CA

If you have current experience with SystemVerilog, OVM, UVM, or VMM ... are a Verification Engineer that has strong SystemVerilog and either UVM/OVM/VMM... more

Aug 22 Digital Design Verification Engineer Texas Instruments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Aug 22 Digital Design Verification Engineer Texas Instrutments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Aug 21 Engineer, Design Verification Results Center Santa Clara, CA

knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) • Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Aug 21 Staff ASIC Verification Engr Job SanDisk Salt Lake City, UT

and work experience with SystemVerilog constrained random testbench development, including UVM/OVM/VMM library and simulator (especially Cadence). •Familiarity with functional... more

Aug 21 ASIC Design Engineer Staff Juniper Networks Sunnyvale, CA

experience • Strong Verilog, or SystemVerilog skills • Strong SystemC or C/C++ and Perl/shell scripts skills. • Knowledge of Synopsys Design Compiler is highly desirable • Must... more

Aug 20 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Aug 19 Engineer, Design Verification Marvell Technology Group Santa Clara, CA

knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) • Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Aug 12 FPGA Engineer Job Leidos Columbia, MD

• 2 years of experiences with Verilog (Systemverilog for verification) hardware ... language (including Systemverilog with OVM/UVM) Leidos Overview:Leidos is an applied... more

Aug 11 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

languages such as VHDL, Verilog, or SystemVerilog. This position provides an exciting opportunity to lead the development and design of state of the art electronic... more

Aug 05 Design Verification Engineer Mindlance San Jose, CA

ASIC design flows Working experience with SystemVerilog and/or UVM Knowledge of wireless communication and good grasp of DSP fundamentals is desirable. **Education:** Preferred:... more

Aug 05 FPGA Verification Engineer Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of... more

Jul 25 Design Verification Engineer Cirrus Logic Austin, TX

SystemVerilog/OVM, UVM, AVM, Vera, e) required. The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog... more

Jul 24 BUS Verification Expert Randstad Technologies - New Cary, NC

UVM/SystemVerilog test bench architecture, SystemVerilog functional coverage, industry standard simulators. EEO Employer: Race, Religion, Color, Sex, Disability, National Origin,... more

Jul 22 WLAN PHY Digital Design Verification Enginee Huntech Consultants Massachusetts

testbench and reference model code in SystemVerilog, C, and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 17 Junior FPGA Engineer Parallel Partners Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Jul 09 Pre-Silicon Verification Engineer Intel Hillsboro, OR

members w/ Intel methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to Intel's backbone (IOSF). Familiar w/ system dependency... more

Jul 08 Senior ASIC Verification Engineer AMD Sunnyvale, CA

development experience (Verilog or SystemVerilog, Perl and C/C++ required) Experience in development and execution of pre-silicon test plans and in development of verification... more

May 30 Engineer, Senior Verification Design Marvell Santa Clara, CA

verification environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high... more

May 15 Senior ASIC Verification Engineer Job Micron Minneapolis, MN

- 5+ Years design verification experience (SystemVerilog, Verilog based). - 1-5 Years of ... Oriented Programming. - Knowledge of SystemVerilog assertions (standard OVL library... more

May 14 Lead Mixed-Signal Pre-Silicon Functional Verification Engineer (E1922125) QUALCOMM San Diego, CA

Functional Verification, OVM, UVM, SystemVerilog, Audio, CODEC, Digital, Mixed-signal, Analog, Lead You will need to login into your profile to apply for this job. If you are... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage ... implementing, debugging, and closing SystemVerilog functional coverage groups. more

Apr 25 Co-Op Engineer Amd | Seamicro Austin, TX

- Experience with SystemVerilog/OVM is a plus. - Requires very strong understanding of computer architecture. - Requires strong communication skills and the ability to work... more

Mar 24 Design Verification Engineer Google Mountain View, CA

functional verification using SystemVerilog Preferred qualifications: * ... such as PCIe, Ethernet, DDR3/4 * Strong SystemVerilog coding skills. * Excellent... more

Mar 10 Sr. Engineer, ASIC Design/Verification Sustainable Recruitment Concepts San Jose, CA

SICs Knowledge of video codec standards such as H.264, MPEG-2 or VP8 Knowledge of new H.265/HEVC standard a big plus Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC,... more

Feb 21 Verification Engineer Altera San Jose, CA

You will write test plans and implement SystemVerilog/UVM based verification ... with coverage driven verification using SystemVerilog test bench development using... more

Feb 06 Senior Staff Design Engineer Xilinx San Jose, CA

· Expert level understanding of Verilog, SystemVerilog, Timing Constraints and Digital Design principles. · Hands on experience of Front End Design and Implementation steps... more

Dec 10 Sr Architect - Verification Acceleration Cadence Design Systems San Jose, CA

CS/CE with 10+ years experience. Expert in SystemVerilog compiler development, code generation and optimizations. Good communication skills and proven leadership in product... more

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