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Jul 30 Junior FPGA Engineer Next Step Systems Chicago, IL

of hardware architecture -Verilog (SystemVerilog is a plus) -Experience of full development cycle of FPGA design -Experience in verification and testing -Should be comfortable... more

Jul 29 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: RTL Coding (Verilog/SystemVerilog) Micro-Architecture ... Synopsys CVS and SVN Perl Scripting SystemVerilog (UVM) STA DMA Designs AXI... more

Jul 29 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Classifiedads.com Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* **Business ... RTL design experience (VHDL/Verilog/SystemVerilog) and/or very strong OO... more

Jul 29 Jr. FPGA Engineer Talent Rif Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Jul 29 Engineer Circuit Design 4(14011994) Northrop Grumman Manhattan Beach, CA

constrained-random verification using SystemVerilog and OVM/UVM, assertions and ... using PSL or SVA, and modeling using C/C++, SystemVerilog, or SystemC. Bachelors of... more

Jul 28 Junior FPGA Engineer Request Technology-stephanie Baker Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Jul 25 Verification Engineers Ee-recruiters Santa Clara, CA

If you have current experience with SystemVerilog, OVM, UVM, or VMM ... are a Verification Engineer that has strong SystemVerilog and either UVM/OVM/VMM... more

Jul 24 BUS Verification Expert Randstad Technologies Cary, NC

in UVMSystemVerilog test bench architecture, SystemVerilog functional coverage, industry standard simulators.x0D Randstad Technologies is an EOE-MFVD and is a wholly owned... more

Jul 24 Design Methodology Engineeer Systems Security Services Austin, TX

coding in HDL languages such as Verilog, SystemVerilog or VHDL Experience with ... methodologies including UVM/OVM, SystemVerilog, functional coverage and... more

Jul 24 BUS Verification Expert Randstad Technologies - New Cary, NC

with bus verification (AXI). Coherency is a plus. Candidate should have working knowledge in UVM/SystemVerilog test bench architecture, SystemVerilog functional coverage,... more

Jul 23 RTL Verification Engineer (Staff/Senior Staff/Principal) SK Hynix Memory Solutions San Jose, CA

Experienced in C/C++, Verilog/SystemVerilog, Perl. Familiar with the latest verification methodologies such as VMM, OVM, and UVM. Experienced in building BFM and C++ models of... more

Jul 23 Design Verification Engineer Altera San Jose, CA

You will write test plans and implement SystemVerilog/UVM based verification ... with coverage driven verification using SystemVerilog test bench development using... more

Jul 22 Graphics Verification Engineer Apple Orlando, FL

Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman ... hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators... more

Jul 22 WLAN PHY Digital Design Verification Enginee Huntech Consultants Massachusetts

testbench and reference model code in SystemVerilog, C, and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 21 Jr. FPGA Engineer Chicago Financial Search Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Jul 17 Lead Software Engineer SJ Cadence Design Systems San Jose, CA

IC process technology and modeling * SystemVerilog * VHDL * Circuit analysis and modeling Must Reference Job Code SJ-9422 Company Information Cadence is the global leader in... more

Jul 14 WLAN Verification Engineer Radiant System Massachusetts

testbench and reference model code in SystemVerilog C and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 14 Logic Design Engineer Marvell Technology Group Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Jul 09 Pre-Silicon Verification Engineer Intel Oregon

members w/ Intel methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to Intel's backbone (IOSF). Familiar w/ system dependency... more

Jul 08 Senior ASIC Verification Engineer AMD Sunnyvale, CA

development experience (Verilog or SystemVerilog, Perl and C/C++ required) Experience in development and execution of pre-silicon test plans and in development of verification... more

Jul 07 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architectureVerilog (SystemVerilog is a plus)Experience of full development cycle of FPGA designExperience in verification and testingShould be comfortable developing... more

Jul 06 Digital Design Verification Engineer Collabera- Niche Massachusetts

digital ASIC verification tests in SystemVerilog and other verification ... testbench and reference model code in SystemVerilog, C, and Matlab in a UVM... more

Jul 02 Digital Design Verification Engineer Collabera Massachusetts

digital ASIC verification tests in SystemVerilog and other verification ... testbench and reference model code in SystemVerilog, C, and Matlab in a UVM... more

Jul 02 Member Consulting Staff Mentor Graphics Indiana

algorithms will be required. Knowledge on SystemVerilog , VHDL, Verilog will be an advantage. Person will be responsible for both internal/external interactions mainly through... more

Jul 02 Member Consulting Staff Mentor Graphics Incorporation Indiana

algorithms will be required. Knowledge on SystemVerilog , VHDL, Verilog will be an advantage. Person will be responsible for both internal/external interactions mainly through... more

Jul 02 Senior level IC Design Verification Engineer (SystemVerilog / UVM) Broadcom Sunnyvale, CA

level IC Design Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... • Deep understanding of HVLs: SystemVerilog/OVM/UVM, RTL design experience... more

Jun 23 Design Verification Engineer - Interconnect Middlesex Community College Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jun 23 Design Verification Engineer - Interconnect Artisan Austin, TX

our products. Responsibilities include: * SystemVerilog testbench development using UVM ... bus protocols, etc. * Verilog and SystemVerilog language and associated... more

Jun 20 Pre-Silicon Functional Validation Hillsboro, OR

members with methodology background (SystemVerilog, OVM, Saola). Must have good debugging skills especially related to backbone (IOSF). PCIE background is a bonus which will help... more

Jun 14 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

languages such as VHDL, Verilog, or SystemVerilog. This position provides an exciting opportunity to lead the development and design of state of the art electronic... more

May 31 ASIC Design Engineer Results Center Santa Clara, CA

environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high speed serial... more

May 30 Engineer, Senior Verification Design Marvell Santa Clara, CA

verification environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high... more

May 14 CPU Design Verification Engineers - Raleigh, NC (E1924229) QUALCOMM Raleigh, NC

Electrical Engineering *LI-SRC Keywords SystemVerilog UVM Simulation Verification You will need to login into your profile to apply for this job. If you are a new user,... more

Apr 28 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage ... implementing, debugging, and closing SystemVerilog functional coverage groups. more

Apr 25 Co-Op Engineer Amd | Seamicro Austin, TX

- Experience with SystemVerilog/OVM is a plus. - Requires very strong understanding of computer architecture. - Requires strong communication skills and the ability to work... more

Mar 24 Video Codec Design Engineer Google Mountain View, CA

at the Register Transfer Level (RTL) using SystemVerilog as well as synthesis and timing closure of digital designs. * Scripting capability in languages such as perl or python as... more

Mar 14 Sr. Design Verification Engineer - Mixed Signal Alliance Solutions Austin, TX

SystemVerilog/OVM, UVM, AVM, Vera, e) required. •The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug... more

Jan 07 Senior Verification Engineer Aba Search San Jose, CA

experience in verification using OVM/UVM/SystemVerilog o Advanced verification methodologies using constrained random, assertion based verification o Experience in putting... more

Nov 30 ASIC Verification Engineer - Boise, Idaho Job Micron Boise, ID

developing Re-Usable Test Benches in SystemVerilog Additional Skills: - Knowledge of SAS/SATA protocols. It has been and will continue to be the policy of Micron to administer all... more

May 31 C++ and System Verilog/UVM Engineer Hire IT People Marlborough, MA

Good programming skills using C++ and SystemVerilog/UVM. Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. more

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