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Oct 18 Digital Design Verification Engineer Texas Instrutments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Oct 18 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 17 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,0 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 17 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Chicago, IL

Hunter Bond FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture * Verilog (SystemVerilog is a plus) * Full development... more

Oct 17 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,000 Hunter Bond Chicago, IL

FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm is currently ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 17 FPGA Engineer/Developer, Verilog, Asic, SystemVerilog, Finance, $200,0 US Local Recruitment Chicago, IL

Description: FPGA Engineer, Verilog, Asic, SystemVerilog Prestigious Global Trading Firm ... of hardware architecture Verilog (SystemVerilog is a plus) Full development... more

Oct 15 Sr Mbr Eng Staff / Firmware / DSP or FPGA / 6-11 Yrs Exp Lockheed Martin Moorestown, NJ

techniques, including knowledge of SystemVerilog and OVM/UVM. Experience in, or knowledge of, hardware/firmware simulation tools. Experience in, or knowledge of, firmware designs... more

Oct 15 RF Engineer Ventures Unlimited San Jose, CA

• working with SystemVerilog and UVM; • verifying mixed signal chips, preferably wireless chips.• At least a master's degree in EE or computer science.I am reachable @... more

Oct 14 RF Engineer Sss Consultants San Jose, CA

• Proficient in working with SystemVerilog and UVM. • Proficient in verifying mixed signal chips, preferably wireless chips. - A master's degree in EE or computer science is... more

Oct 13 Pre-Si Verification Engineer Intel Israel, PR

using automated tools - mainly Specman or SystemVerilog. - Develop SOC verification ... - Knowledge of the 'e' (Specman) or SystemVerilog and Verilog languages - Clear... more

Oct 13 Digital Ic Design Engineer Career Development Partners Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Oct 09 I163 Design Engineer Marvell Technology Group Santa Clara, CA

esign, integration and verification of ARM based wireless networking devices. • Design and verify at module, cluster and top level Verilog/SystemVerilog • Participate in FPGA... more

Oct 08 Digital Verification -- SystemVerilog Functional Coverage Implementation Artech Information Systems Austin, TX

Job Title: Digital Verification - SystemVerilog Functional Coverage Implementation ... implementing, debugging, and closing SystemVerilog functional coverage groups. more

Oct 07 ASIC Verification Engineer Job Micron Boise, ID

developing Re-Usable Test Benches in SystemVerilog Additional Skills: - Knowledge of SAS/SATA protocols. It has been and will continue to be the policy of Micron to administer all... more

Oct 06 IC Verification Engineer Fusion408 Santa Clara, CA

Engineer who is well versed with SystemVerilog, OVM, and C++. This is a highly ... -UVM -BFM What you will be doing. * Utilize SystemVerilog experience in a C++ environment... more

Oct 03 Applications Engineer - Verification Tabula Santa Clara, CA

3+ years of industry experience Verilog/SystemVerilog coding experience UVM/OVM Assertion-based verification Creation of verification environments that implement constrained... more

Oct 02 Principal Verification Engineer (systemverilog / Uvm) Broadcom Sunnyvale, CA

Title Principal Verification Engineer (SystemVerilog / UVM)* Business Unit Broadband ... RTL design experience (VHDL/Verilog/SystemVerilog) and/or very strong OO... more

Sep 26 MicroProcessor Verification - Pre Silicon Computer Task Group Austin, TX

programming using languages such as C++ and SystemVerilog. * Experience in scripting languages such as Perl. * Working knowledge of hardware description language (HDL) (VHDL or... more

Sep 24 FPGA Verification Contractor Fidus Systems San Jose, CA

Specifically, you have strong knowledge in: SystemVerilog Verilog and VHDL Hardware Description language Modelsim/Questa Simulation tools Xilinx ISE Tools Xilinx Spartan6 family... more

Sep 21 Jr. FPGA Engineer Financial Services Institution - Finance Industry Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Sep 21 Digital Design Verification Engineer Texas Instruments Dallas, TX

and flow. * Develop Verification plans, SystemVerilog testscases and verification ... using advanced verification methodologies in SystemVerilog. * Drive new and improved... more

Sep 17 Postdoctoral Scholar Pennsylvania State University Pennsylvania

C/C++/C#/Java; Python; ROS; Verilog or SystemVerilog; VHDL; Open CV and Open CL; and Linux. Candidate selected may be subject to a government security investigation. This is a one... more

Sep 17 Engineer, Verification Design Results Center Santa Clara, CA

h knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage) •Familiarity with SystemVerilog/UVM/formal verification/emulation is... more

Sep 12 Sr Verification Engineer Job SanDisk Milpitas, CA

of assertions and testbench development in SystemVerilog and UVM. Support of full-chip verification, including digital circuits. This position requires a Bachelors degree in... more

Sep 10 Design Verification Engineer (NCG) Altera San Jose, CA

top and IP level design/verification using SystemVerilog/UVM. You are expected to generate UVM/SV code to match design behavior. Other new methods of verification will also be... more

Sep 09 Digital Design and Verification Engineer Linear Technology Colorado Springs, CO

areas: • RTL design in Verilog and SystemVerilog. • Architecture specification including familiarity with microprocessor and SoC architectures. • Validation of software and... more

Sep 04 Jr. Hardware Engineer Eagle Technical Staffing Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Sep 04 Senior MTS Design Verification Engineer Amd | Seamicro Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Senior MTS Design Verification Engineer AMD Sunnyvale, CA

• Strong expertise with Verilog/SystemVerilog and OVM/UVM • Experience architecting and creating testbenches from scratch, both as the unit and system level • Experience with... more

Sep 03 Staff Digital Design Engineer Silicon Laboratories Austin, TX

Skills, and Abilities: Verilog and SystemVerilog RTL and behavioral modeling skills. Working knowledge of a logic synthesis tool such as Synopsys Design Compiler or Cadence RTL... more

Aug 20 Staff IC Design Engineer Avago Technologies Colorado Springs, CO

but not limited to: • RTL Coding (Verilog/SystemVerilog) • Micro-Architecture • ... • SystemVerilog (UVM) • STA • DDR3/DDR4 (All Variations) • ONFI • AXI Bachelors... more

Aug 11 Lead Digital Hardware and FPGA Engineer Mitre Massachusetts

languages such as VHDL, Verilog, or SystemVerilog. This position provides an exciting opportunity to lead the development and design of state of the art electronic... more

Aug 05 Design Verification Engineer Mindlance San Jose, CA

ASIC design flows Working experience with SystemVerilog and/or UVM Knowledge of wireless communication and good grasp of DSP fundamentals is desirable. **Education:** Preferred:... more

Jul 29 Jr. FPGA Engineer Talent Rif Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

Jul 22 WLAN PHY Digital Design Verification Enginee Huntech Consultants Massachusetts

testbench and reference model code in SystemVerilog, C, and Matlab in a UVM ... digital ASIC verification tests in SystemVerilog and other verification... more

Jul 08 FPGA Engineer Request Technology Chicago, IL

of hardware architecture Verilog (SystemVerilog is a plus) Experience of full development cycle of FPGA design Experience in verification and testing Should be comfortable... more

May 30 Engineer, Senior Verification Design Marvell Santa Clara, CA

environments, preferably using SystemVerilog (UVM, OVM, VMM). - Proficient in C programming as well as some scripting skills. - Knowing NAND flash memory and high speed serial... more

May 14 Lead Mixed-Signal Pre-Silicon Functional Verification Engineer (E1922125) QUALCOMM San Diego, CA

Keywords Functional Verification, OVM, UVM, SystemVerilog, Audio, CODEC, Digital, Mixed-signal, Analog, Lead You will need to login into your profile to apply for this job. If you... more

Mar 24 Video Codec Design Engineer Google Mountain View, CA

at the Register Transfer Level (RTL) using SystemVerilog as well as synthesis and timing closure of digital designs. * Scripting capability in languages such as perl or python as... more

Oct 22 Design Verification Engineer Verilab Hillsboro, OR

Significant project-based experience using SystemVerilog, Specman/e, SystemC or Vera Project-based experience using UVM, OVM, AVM, VMM, and/or eRM BS/MS/PhD in Engineering or... more

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