Verilog jobs
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| Nov 22 | Sr. Digital Design Engineer | Synaptics | Santa Clara, CA |
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synthesis, and verification of RTL code (Verilog/VHDL) for digital sub-systems of ... skills and experience at the RTL-level (Verilog/VHDL).?? Experience in using IC... more |
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| Nov 22 | Sr. Flash Memory Design Engineer | San Jose, CA | |
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including functional block design using verilog and synthesis tools. ? Define test modes and planning for full chip verification. ? Transfer circuit design to physical layout... more |
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| Nov 22 | Electrical Engineer - Embedded Systems/C Programming /FPGA | Think Resources | Boston, MA |
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to have related MS or Phd-> C++/C, VHDL/Verilog-> Hardware design ? ability to ... developing FPGA logic using VHDL and-or Verilog Please explain your experience has a... more |
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| Nov 22 | Senior Circuit Design Engineer - Standard Cell | Broadcom | Tempe, AZ |
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design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys, spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based... more |
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| Nov 22 | Hardware Systems Electrical Engineer | Siemens | Bartlesville, OK |
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ovative/intuitive ability in analog design?Knowledge of embedded processor design and associated digital circuits?Experience in VHDL or VERILOG FPGA design strongly... more |
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| Nov 22 | Applications Engineer | Altera | San Jose, CA |
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Experience debugging Verilog / VHDL. Experience with hardware, IP bring-up and data collection methodologies. Working knowledge of test equipment and system level debug. more |
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| Nov 22 | Sr Staff Memory Design Engineer | Broadcom | Tempe, AZ |
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with Unix shell languages; knowledge of verilog modeling; familiarity with layout verification tools, design rules, and rule decks. Location:United States-Arizona-Tempe Position... more |
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| Nov 22 | Senior Circuit Design Engineer - Standard Cell | Broadcom | Irvine, CA |
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design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys, spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based... more |
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| Nov 22 | Sr. Design Verification Engineer | Synergy Seven | Chandler, AZ |
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compliance testing . Proficient in System Verilog and random constraint methodology . ... to Design Verification using System Verilog . Proficient in Synopsys VCS . more |
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| Nov 22 | SR. DESIGN VERIFICATION ENGINEER | Mainz Brady Group | Hillsboro, OR |
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compliance testing . Proficient in System Verilog and random constraint methodology . ... to Design Verification using System Verilog . Proficient in Synopsys VCS . more |
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| Nov 22 | Embedded Firmware Engineer - FPGA Programmer - ASIC, Hardware | Cybercoders | Brookings, SD |
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Linux, Windows, Xilinx, Altera, ASIC, VHDL, Verilog - Working Knowledge in ST7100, ATSC, DVB, H.264, MPEG/PSI/PSIP - Power Supplies, Video/Audio, DSP, PC Board Layout,... more |
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| Nov 21 | Verification Engineer | Denali Software | Austin, TX |
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experience with design IP coded in Verilog Test builder experience Exposure to ... analysis Debug expertise in tool flow for Verilog based designs and netlists... more |
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| Nov 21 | Read Channel Modeling Engineer | LSI LOGIC | Longmont, CO |
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Knowledge of Verilog and/or VHDL (System Verilog is a plus) Excellent technical ... include developing and verifying Verilog functional RTL and gate level... more |
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| Nov 21 | Sr Staff Memory Design Engineer | Broadcom | Minneapolis, MN |
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with Unix shell languages; knowledge of verilog modeling; familiarity with layout verification tools, design rules, and rule decks. City : Minneapolis State : Minnesota Country... more |
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| Nov 21 | Software Engineer | Denali Software | Sunnyvale, CA |
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communication skills.Experience in Unix and Verilog or VHDLstrong analytical and problem solving skillsStrong C (or C++) programming skillsBSEE/CEStrong Plus: Knowledge of... more |
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| Nov 21 | Sr Staff Memory Design Engineer | Broadcom | Tempe, AZ |
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with Unix shell languages; knowledge of verilog modeling; familiarity with layout verification tools, design rules, and rule decks. City : Tempe State : Arizona Country :... more |
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| Nov 21 | High Speed : CPU Designer | Modicom | San Jose, CA |
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been through the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). --Should... more |
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| Nov 21 | Field Application Engineer | Denali Software | Sunnyvale, CA |
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with 5+ years of relevant experience Strong Verilog Skills Excellent verbal and written presentation and communications skills Strong interest and understanding of design... more |
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| Nov 21 | Senior Circuit Design Engineer - Standard Cell | Broadcom | Tempe, AZ |
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design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys, spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based... more |
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| Nov 21 | Senior Circuit Design Engineer - Standard Cell | Broadcom | Irvine, CA |
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design, place & route, Calibre, Hercules, Verilog/VHDL, Synopsys, spice simulation, verification, Cadence layout, Cadence schematic capture, Cadence skill language, Unix based... more |
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| Nov 20 | Design Engineer I | SanDisk | Milpitas, CA |
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machine in verilog code and synthesize the verilog code into gate level circuits with ... and oscilloscopes Develop test vectors in verilog and HSPICE to verify functionality... more |
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| Nov 20 | Senior ASIC Design Engineer - Storage | Modicom | San Jose, CA |
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the architecture of new product --Verilog RTL design and coding --Synthesis, ... such as P1394/ATA/ATAPI --Familiar with Verilog RTL design --Familiar with Verilog... more |
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| Nov 20 | Post Doctoral Fellow | Carnegie Mellon University | Pittsburgh, PA |
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analog behavioral modeling languages (e.g., Verilog-A, Verilog-AMS); Candidate must be ... systems-level modeling in Verilog-A and use of Cadence for... more |
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| Nov 20 | CPU Verification Engineer | Modicom | Santa Clara, CA |
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environments --Developed testbenches in Verilog and C PLI --Experienced with the ... VCS). --Created and debugged tests for Verilog designs --Utilized scripting... more |
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| Nov 20 | CPU Logic Design Engineer (Raleigh | QUALCOMM | Cary, NC |
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(knowledge of ARM ISA is a plus) Verilog design entry preferred Excellent oral and written communication skills Ability to work in a team environment Excellent verbal and... more |
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| Nov 20 | Embedded Firmware Engineer - FPGA Programmer - ASIC, Hardware | Cybercoders | Brookings, SD |
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Linux, Windows, Xilinx, Altera, ASIC, VHDL, Verilog - Working Knowledge in ST7100, ATSC, DVB, H.264, MPEG/PSI/PSIP - Power Supplies, Video/Audio, DSP, PC Board Layout,... more |
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| Nov 20 | Grad Intern: FPGA Engineer | Intel | Folsom, CA |
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written communication skills - Knowledge of Verilog, System Verilog and/or VHDL - Tcl/Perl scripting experience and/or Linux shell* programming would be an added advantage Job... more |
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| Nov 20 | Grad Intern: FPGA Engineer | Intel | Hillsboro, OR |
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written communication skills - Knowledge of Verilog, System Verilog and/or VHDL - Tcl/Perl scripting experience and/or Linux shell* programming would be an added advantage Job... more |
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| Nov 20 | Graduate Intern Technical | Intel | Phoenix, AZ |
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Perl, Verilog/VHDL, and UNIX. FPGA, System Verilog, and/or Specman knowledge a plus. Video codec, cryptography, or graphics knowledge a plus. Job Category : Engineering Primary... more |
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| Nov 20 | Design Engineer I | SanDisk | Milpitas, CA |
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Some experience in using circuit and or verilog simulator. SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched... more |
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| Nov 20 | Firmware Design Engineer - Optoelectronic Control | Infinera | Sunnyvale, CA |
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C programming skills. Knowledge of Verilog and FPGA-based control loops. Knowledge of control loop design and analysis tools Familiarity with equipment control and data... more |
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| Nov 20 | Component Design Engineer | Intel | Folsom, CA |
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methodologies including: Verilog, System Verilog, Java, Perl, object oriented constructs, VCS/Modelsim simulators, System C - Knowledge of PC Architecture - Excellent... more |
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| Nov 20 | Sr. Electrical Engineers (Debug) | Volt Information Sciences | Austin, TX |
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and knowledge of PC system architecture. Verilog RTL design experience is a plus. In depth experience w/ Hypertransport, DDR memory interfaces, PCIe, PCI, and/or PC I/O busses and... more |
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| Nov 20 | CPU Logic Design Engineer (Raleigh | QUALCOMM | Cary, NC |
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(knowledge of ARM ISA is a plus) Verilog design entry preferred Excellent oral and written communication skills Ability to work in a team environment Additional Skills Excellent... more |
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| Nov 20 | Validation Engineer | Intel | Folsom, CA |
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tools, Specman*, Debussy* and System Verilog* - Responsible for creation of tools, test environments, tests and scripts - Performing modeling and simulation, random and focused... more |
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| Nov 20 | Design Verification Engineer | Sriven Infosys | Chandler, AZ |
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in compliance testing Proficient in System Verilog and random constraint methodology ... to Design Verification using System Verilog Proficient in Synopsys VCS... more |
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| Nov 20 | Principal Systems Engineer | Broadcom | Sunnyvale, CA |
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design principles and some HDL (VHDL/Verilog) literacy.* DSP experience is desirable.* RF experience is desirable.* Must have excellent written and oral communication skills.*... more |
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| Nov 20 | Design Engineer I | SanDisk | Milpitas, CA |
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digital simulation tools such as HSPICE and VERILOG is a must. The designer will participate in verification of silicon using lab equipments and testers and needs to create detail... more |
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| Nov 20 | Validation Intern | Intel | Santa Clara, CA |
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Standard Products (ASSP) using System Verilog Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include:... more |
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| Nov 20 | Senior Verification Engineer - Xbox | Microsoft | Mountain View, CA |
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implementing many of those test plans using Verilog and 'C'. Additionally, the candidate ... verification experience using both C and Verilog languages Other skills needed to be... more |
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